IDT 89HPES12N3, Руководство пользователя

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Notes
PES12N3 User Manual 2 - 1 June 7, 2006
Chapter 2
Clocking, Reset, and
Initialization
Introduction
The PES12N3 has two differential reference clock inputs that are used internally to generate all of the
clocks required by the internal switch logic and the SerDes. While not required, it is recommended that both
reference clock input pairs be driven from a common clock source. There are no skew requirements
between the reference clock inputs.The frequency of the reference clock inputs may be selected by the
Reference Clock Mode Select (REFCLKM) input.
Each of the reference clock differential inputs feeds six on-chip PLLs. Each PLL generates a 2.5 GHz
clock which is used by four SerDes lanes and produces a 250 MHz core clock.The 250 MHz core clock
output from one of the six internal PLLs is used as the system clock for internal switch logic.
Initialization
A boot configuration vector consisting of the signals listed in Table 2.2 is sampled by the PES12N3
during a fundamental reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require configuration via an external serial EEPROM. The external serial EEPROM allows
modification of any bit in any software visible register. See Chapter 7, SMBus Interfaces, for more informa-
tion on the serial EEPROM.
The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a fundamental reset. The signals that may be over-
ridden are noted in Table 2.2.
The state of all of the boot configuration signals in Table 2.2 sampled during the most recent cold reset
may be determined by reading the PA_SWSTS register.
REFCLKM Description
0 100 MHz reference clock input.
1 125 MHz reference clock input.
Table 2.1 Reference Clock Mode Encoding