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3-20 Processor Interface
3.15 Error Handling and Reporting
3.15.1 Processor transfer type errors
The processor interface may be enabled to detect and report processor transfer attribute errors.
On a processor read, if a transfer attribute error is detected, the processor interface will complete the
access and return all 1’s (that is, each bit in the processor data bus will be set to 1) with the transfer
acknowledge assertion.
On a processor write, if a transfer attribute error is detected, the processor interface will complete the
access and discard the write data.
On a processor Address Only cycle, the transfer size and transfer burst signals are ignored for error detec-
tion.
If detection is enabled via ERREN1[0], the error will be logged by setting ERRDET1[0], the associated pro-
cessor address will be logged in CPUERAD[0:31], the associated processor transfer attributes will be
logged in CPUERAT[0:7], and if enabled via PRIFOPT1[1], the machine check output (MCP_N) will be
asserted for a minimum of two clock cycles.
All subsequent error logging is disabled until the current error condition is cleared. Errors can be cleared by
writing a 1 to ERRDET1[0].
The following constitute processor transfer attribute errors:
• Any processor read or write with TT[0:3] 1010 or 1110. This includes ecowx, eciwx, and reserved
transfer type encodings TT[0:4] = 10101, 11101, 1011x
• Any processor read or write with an invalid address and transfer size alignment. All valid combina-
tions of processor address (A[29:31]), transfer size (TSIZ), and transfer bursts (TBST_N) are
listed below. Any processor accesses aligned to any other boundaries will be detected as an error.
• Any processor read or write to DCR address space which is not 4 bytes and aligned to a 4 byte bound-
ary.
• Any processor read or write to DCR address space for which no DCR slave responds. This is basically
a configuration read or write which times out on the internal DCR bus. DCR time-out occurs when no
DCR slave responds within 16 clocks from the time the DCR access was initiated on the internal DCR
bus.
Table 20. Valid Address, TBST_N, and TSIZ Combinations
A[29:31] TBST_N TSIZ[0:2] A[29:31] TBST_N TSIZ[0:2]
000 1 010 //burst 010 0 010 //2 byte a2
000 0 001 //1 byte a0 100 0 010 //2 byte a4
001 0 001 //1 byte a1 101 0 010 //2 byte a5
010 0 001 //1 byte a2 110 0 010 //2 byte a6
011 0 001 //1 byte a3 000 0 011 //3 byte a0
100 0 001 //1 byte a4 001 0 011 //3 byte a1
101 0 001 //1 byte a5 100 0 011 //3 byte a4
110 0 001 //1 byte a6 101 0 011 //3 byte a5
111 0 001 //1 byte a7 000 0 100 //4 byte a0
000 0 010 //2 byte a0 100 0 100 //4 byte a4
001 0 010 //2 byte a1 000 0 000 //8 byte a0