IBM CPC700, Руководство пользователя

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3-18 Processor Interface
3.13 CPC700 Response for PCI to Memory Accesses
The following table corresponds to the state of the PLB Address bus as it relates to the associated snoop
cycle on the processor address bus for a given cycle (which may or may not be pipelined) and the corre-
sponding processor interface response. NOTE: for any of the transactions listed, the internal memory con-
troller interface may be idle or busy (servicing a processor-Mem write buffer flush or finishing the data
tenure of a PCI or processor to memory access). If the internal memory controller interface(MCIF) is busy,
the address for the PCI to memory access is placed on the MCIF as soon as possible. The data tenure for
the requested access will execute on the MCIF following the completion of the in progress data tenure.
Once the PCI request is accepted by the processor interface, data will be transferred at the earliest avail-
able opportunity within the guidelines of the PLB specification. For burst cycles crossing a cache line
boundary, it is necessary to snoop early enough to perform burst terminate on PLB should it be necessary.
3.14 Processor to DCR/Configuration Space
Access to the CPC700 processor interface and the memory controller is through a dedicated on chip bus
called the Device Configuration Register Bus (DCR Bus). DCR access uses an indirect addressing method
whereby a configuration address register and a configuration data register are used to address all of the
configuration registers in the processor interface and the memory controller. Addresses used for access to
these registers are listed in Table 18.
Table 17. Processor Interface Response to PLB Transactions
PLB
(Snooper) Proc-Mem
Write Buffer Processor
L1
Response
Mem R/W Miss, Empty Clean AdrAck PLB when memory controller acknowledges, buffer
data to/from Memory for transfer to/from PLB.
Mem R/W Miss, Allocated Clean AdrAck PLB when memory controller acknowledges, buffer
data to/from Memory for transfer to/from PLB.
Mem R/W Hit D.C. Rearbitrate PLB, High Priority write for processor-Mem W.B.
flush.
Mem R/W Miss, Empty Artry_ Rearbitrate PLB, grant to processor if requesting.
Mem R/W Miss, Allocated Artry_ Rearbitrate PLB, High Priority write for processor-Mem W.B.
flush, grant to processor if requesting.
Mem R/W
Burst - Cross-
ing cache line Hit D.C. Burst Terminate PLB, High Priority write for processor-Mem
W.B. flush.
Mem R/W
Burst - Cross-
ing cache line Miss, Empty Artry_ Burst Terminate PLB, grant to processor if requesting.
Snoop processor L1 in advance to ensure PLB burst terminat-
ed at end of cache line.
Mem R/W
Burst - Cross-
ing cache line Miss, Allocated Artry_ Burst Terminate PLB, High Priority write for 60x-Mem W.B.
flush, grant to processor if requesting.
Snoop processor L1 in advance to ensure PLB burst terminat-
ed at end of cache line.