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10-8

Interrupt Controller

10.5.7 UICMSR — UIC Masked Status Register

Figure 62. UICMSR -- UIC Masked Status Register

This read-only register contains the result of masking the UICSR with the UICER. Reading this register
instead of the actual UICSR will eliminate the need for the software to read and apply the enable mask to
the contents of the Status register in order to determine which enabled bits are active.

When an interrupt bit is configured for level sensitivity, and a clear is attempted on the UICSR, the UICSR
bit will not be cleared if the incoming interrupt signal is still at the asserted polarity. In this configuration the
interrupt signal must be reset before the UICSR can be successfully cleared.

10.5.8 UICVCR — UIC Vector Configuration Register

Figure 63. UICVCR -- IUC Vector Configuration Register

The most significant 30 bits of this register will contain the vector base address. The lowest bit will contain
the priority ordering bit, which determines which end of the Status register is higher priority. The second
least significant bit of this register is unused.

The vector base address should be set by software to the base address for the interrupt handler routines
associated with each interrupt. The vector base address set in the UICVCR is used when calculating the
interrupt vector. The two least significant bits of this address are always assumed to be ’00’, so the vector
base address will always be on a full word boundary. See the UICVC register description for more informa-
tion on vector address generation.

The priority ordering bit is a single bit that is used to designate whether the highest priority interrupt in the
UICSR is either Interrupt[0] or Interrupt[31]. If set to a 0, this bit indicates that Interrupt[31] is the highest
priority interrupt. If set to a 1, this bit indicates that Interrupt[0] is the highest in priority. The bit in the UICSR
that is closest to the highest priority bit, and is programmed in the UICCR as an INT interrupt, will have the
second highest priority and the priority continues to decrease to the lowest priority at the other end of the
UICSR. This register is not readable, if attempted 0s will be returned.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

MSB

LSB

Interrupt [0] Masked
Interrupt [1] Masked
Interrupt [2] Masked
Interrupt [3] Masked

Interrupt [4] Masked

• • •

• • •

Interrupt [31] Masked

• • •

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

MSB

LSB

Priority Ordering Bit

Unused

Interrupt Vector Base Address

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Содержание CPC700

Страница 1: ...CPC700 Memory Controller and PCI Bridge User s Manual Version 1 1 Issue Date 3 22 00 Preliminary...

Страница 2: ...ation contained herein Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties The products described in thi...

Страница 3: ...esses 3 8 3 8 Processor Address Only Cycles 3 10 3 9 Processor Bus Arbiter 3 11 3 10 Broadcast Snoop Cycles 3 12 3 11 Byte Swapping 3 13 3 11 1 Processor to PLB PCI Byte Swapping 3 13 3 11 2 PCI to Me...

Страница 4: ...1 4 1 Features 4 1 4 2 Memory Controller Block Diagram 4 2 4 3 Memory Controller Registers 4 3 4 4 Memory Access Arbiter 4 4 4 5 SDRAM 4 4 4 5 1 Initialization Sequence 4 5 4 5 2 Page Mode Accesses 4...

Страница 5: ...ter 4 58 Chapter 5 PCI Interface 5 1 5 1 Overview 5 1 5 2 Features 5 1 5 3 PCI Bridge Block Diagram 5 2 5 4 PCI Interface Registers 5 3 5 5 PCI Interface Address Maps 5 4 5 5 1 PLB Address Map 5 4 5 5...

Страница 6: ...er PCICFGADR 5 26 5 9 2 3 PCI Configuration Data Register PCICFGDATA 5 26 5 9 3 PCI Interface Configuration Registers 5 26 5 9 3 1 PCI Vendor ID Register 5 27 5 9 3 2 PCI Device ID Register 5 27 5 9 3...

Страница 7: ...5 48 5 11 1 3 Other Registers that must be Initialized 5 50 5 11 1 4 Target Bridge Initialization 5 50 Chapter 6 Clock Power Management and Reset 6 1 6 1 CPC700 Clock Control 6 1 6 1 1 PLL Tuning 6 1...

Страница 8: ...rol Register 8 14 8 5 Interrupts 8 15 8 6 General Considerations 8 16 Chapter 9 General Purpose Timers 9 1 9 1 Introduction 9 1 9 1 1 GPT Registers 9 1 9 1 2 Programmability 9 2 9 2 Mode of Operation...

Страница 9: ...10 8 10 5 9 UICVR UIC Vector Register 10 9 Chapter 11 JTAG 11 1 Chapter 12 Processor Local Bus PLB 12 1 12 1 PLB Master Priority Assignment 12 1 12 2 PLB Arbiter Registers 12 2 12 2 1 PLB Arbiter Cont...

Страница 10: ...Table of Contents x Table of Contents...

Страница 11: ...1 CPU Write Write 4 22 Figure 22 PCI Continuous Read Burst 4 23 Figure 23 Continuous Write Burst 4 24 Figure 24 PCI Short Burst Read PCI Short Burst Read 4 25 Figure 25 PCI Short Burst Read PCI Short...

Страница 12: ...9 9 Figure 56 UICSR UIC Status Register 10 5 Figure 57 UICSRS UIC Status Register Set 10 5 Figure 58 UICER UIC Interrupt Enable Register 10 6 Figure 59 UICCR UIC Critical Interrupt Register 10 6 Figur...

Страница 13: ...alid Address TBST_N and TSIZ Combinations 3 20 Table 21 Memory Controller Register Addressing 4 3 Table 22 Offsets for Memory Controller Registers 4 3 Table 23 Determining Maximum Page Size 4 5 Table...

Страница 14: ...ration Access Register 6 8 Table 68 PLL Tuning Control Register 6 8 Table 69 Strapping Pin Register 6 9 Table 70 UART Core Configuration Registers 7 3 Table 71 Summary of UART Registers Big Endian Not...

Страница 15: ...egister Addressing 14 1 Table 105 Offsets for Processor Interface Registers 14 1 Table 106 Memory Controller Register Addressing 14 2 Table 107 Offsets for Memory Controller Registers 14 2 Table 108 P...

Страница 16: ...Tables xvi List of Tables...

Страница 17: ...herals PCI Revision 2 1 Compliant Interface 32 bit 25 to 66 MHz PCI Bus Interface may be configured to operate synchronously or asynchronously to the processor bus synchronous clock is limited to 33 M...

Страница 18: ...o independent IIC ports If the design requires additional functionality an integrated peripheral bus supports 8 16 32 or 64 bit device operations for external peripherals This bus also sup ports the B...

Страница 19: ...0 User s Manual Preliminary 1 3 Figure 1 System Block Diagram 60x 7xx Bus 2 UARTs 2 I2C Interrupts PCI Devices PCI Bus SDRAM PCI arbiter CPC700 Timers PowerPC 60x 7xx Processor ROM SRAM External Perip...

Страница 20: ...o primary busses the Processor Local Bus PLB and the On Chip Peripheral Bus OPB The PLB operates at the same frequency as the local processor bus The OPB operates at half of the frequency of the PLB P...

Страница 21: ...ary resources independently This map ping can be performed solely from the processor side or from a combination of the processor and the PCI side This mechanism lets the same fixed secondary resources...

Страница 22: ...7FFF FFFF 2GB PCI Core Space 8000 0000 FF4F FFFF 2GB 11MB PCI Memory 8000 0000 F7FF FFFF PCI I O F800 0000 F800 FFFF Reserved F801 0000 F87F FFFF PCI I O F880 0000 FBFF FFFF Reserved FC00 0000 FEBF F...

Страница 23: ...figurations The memory controller supports up to five banks five Chip Select outputs Bank 0 is dedi cated to Boot ROM while banks 1 4 may be programmed to support either SDRAM ROM SRAM or external per...

Страница 24: ...support 32 or 64 bit data bus widths Support for mixing ECC and non ECC DIMMs in the same system ECC checking may be disabled UART The CPC700 contains two UARTs that provide two wire full duplex seri...

Страница 25: ...cations link IIC Bus Interface The CPC700 provides two fully independent IIC bus interfaces The IIC bus is a two wire bidirectional open drain low speed serial interface Both the serial clock SCL and...

Страница 26: ...ted Synchronous level sensitive Synchronous edge capture Asynchronous Choice of edge or level sensitive triggering is programmable Polarity is programmable for all types Prioritized interrupt handler...

Страница 27: ...well as for the support of board level testing and debug The following JTAG commands are supported by the CPC700 JTAG TAP controller 1 EXTEST 2 SAMPLE PRELOAD 3 BYPASS 4 CLAMP 5 IDCODE 6 USERCODE The...

Страница 28: ...1 12 CPC700 User s Manual Preliminary...

Страница 29: ...parity pin to processor data paths is as follows DP0 DH0 DH7 DP2 DH8 DH15 DP3 DH16 DH23 DP4 DH24 DH31 If the internal PCI arbiter is enabled these signals carry the PCI Request inputs 2 5 providing fo...

Страница 30: ...he bus and acts as an output when the CPC700 initiates a snoop cycle on behalf of a PCI master access to local memory BR_N Low I Bus Request Processor bus request from the local processor BG_N Low O B...

Страница 31: ...actively driven indicates the driving device has decoded its address as the target of the current access IDSEL High I Initialization Device Select Used as a chip select during configuration read and...

Страница 32: ...rbiter will be disabled GNT0_N REQ_N Low O Grant 0 Request When the internal PCI arbiter is enabled this signal functions as the Grant 0 output to another PCI master device When the internal PCI arbit...

Страница 33: ...ECC or the additional DQM lines are governed by a pin strapping option DQM7 corresponds to Memory Data Lane 7 MA 12 0 High O Memory Address 12 0 Memory address bus Memory address bit 10 also functions...

Страница 34: ...nd hold the higher order address bits of the ROM peripheral address The ROM_ALE signal may be used as a latch enable for an external address bus latch to capture those signals ROM_READY High I ROM Rea...

Страница 35: ...errupt the processor These interrupt inputs are asynchronous and may be programmed to cause an interrupt on either the rising or falling edge IRQ_OUT_N Low O Interrupt Output Interrupt output to the l...

Страница 36: ...DI2_N Low I Driver Inhibit 2 The driver inhibit 2 pin is only used during manufacturing test and must be high during functional operation There is an internal 20K pull up to 3 3V on this signal Eithe...

Страница 37: ...port 32 Byte Write Buffer to memory 32 Byte Write Buffer to PLB lwarx stwcx support reservation cancelling snoops Address Only cycle support Machine Check Interrupt request input MCP_REQ for processor...

Страница 38: ...e various configuration registers located within the processor interface Register Address R W Description PIFCFGADR FF50_0000 R W Processor Interface Configuration Address Register PIFCFGDATA FF50_000...

Страница 39: ...Ending Address PLBMTLSA2 28 R W Processor PLB Master Byte Swap Region 2 Starting Address PLBMTLEA2 2C R W Processor PLB Master Byte Swap Region 2 Ending Address PLBMTLSA3 30 R W Processor PLB Master...

Страница 40: ...nge Description Processor Address 0 to 2G 1 h00000000 h7FFFFFFF System Memory PCI accesses to this range will target system memory and be snooped Snooping can be dis abled for a particular region usin...

Страница 41: ...C700 Response for Proc to Memory CPC700 Response for Proc to PLB 0000 Clean block or lwarx Address only Assert AACK_N No other response No PLB transaction 0001 Write with flush SBW or burst Memory wri...

Страница 42: ...snooped in addition to the processor s L1 cache Write Buffer Once data is posted in the processor to memory write buffer it is flushed to memory at the earliest available opportunity In general the p...

Страница 43: ...N to the processor data will be transferred at the earliest available opportunity Note In Table 8 the state of the processor to PLB write buffer is a don t care Table 9 lists the corresponding memory...

Страница 44: ...nterface buffer to expedite de allocation of the primary 32 byte write buffer which allows the processor to post a maximum of two single beat write cycles for transfer to the PLB All processor to PLB...

Страница 45: ...p er PLB Rd Allocated Allocated Idle Continue to attempt write on PLB initiate read on PLB when write completes PLB Rd Allocated Allocated Snoop Pending ARTRY_N CPU grant to snooper continue to attemp...

Страница 46: ...ndary 2 8 byte read w byte enables Request W0 Read data transfer to CPU_DATA 0 31 Request W1 Read data transfer to CPU_DATA 32 63 Read 32 Bytes 8 Word Line 8 word line read consisting of 8 PLB data ph...

Страница 47: ...when the processor initiates a bus transaction while parked as an implicit bus request which was granted and maintains the rotating priority accordingly In general the priority is controlled by a rota...

Страница 48: ...d and snooped in the processor s L1 cache before allowing the access Snoop cycles to the processor are gener ated on behalf of the PCI interface by the internal snooper The following table lists the c...

Страница 49: ...Endian No swapping mech anism is available for this data path 3 11 1 Processor to PLB PCI Byte Swapping Byte swapping can occur on the processor to PLB data path for both read and write cycles initia...

Страница 50: ...to PLB Big Endian to Little Endian Byte Swapping Processor PLB Byte PLB 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 6 7 Processor PLB Byte PLB 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 6 7 Processor PLB Byte PLB 0...

Страница 51: ...rdering within bytes is preserved such that PCI_BYTE0 7 0 corresponds to CPU MEM_BYTE0 0 7 For example if PCI_BYTE0 7 0 22 then CPU MEM_BYTE0 0 7 22 The following figure illustrates the byte preservat...

Страница 52: ...is the LSB as seen from the local processor Using the default byte lane preservation method when the PCI accesses the same memory location the value will appear on the PCI bus as x 78563412 where byt...

Страница 53: ...data from the PCI to memory is buffered in a 32 byte write buffer and when possible packed into 8 byte doubleword aligned transfers before being written to memory PCI to memory write cycles are buff e...

Страница 54: ...Bus DCR Bus DCR access uses an indirect addressing method whereby a configuration address register and a configuration data register are used to address all of the configuration registers in the proc...

Страница 55: ...ontroller Config data register xFF50_000C Table 19 CPC700 Response to Processor Interface Configuration Transactions Proc Proc Mem Write Buffer Proc PLB Write Buffer PLB SLV Snoop Response Conf Rd Dea...

Страница 56: ...nsfer attribute errors Any processor read or write with TT 0 3 1010 or 1110 This includes ecowx eciwx and reserved transfer type encodings TT 0 4 10101 11101 1011x Any processor read or write with an...

Страница 57: ...tect and report flash write errors for processor to memory write transfers which target the ROM Peripheral controller as well as banks for which flash writes are not enabled This event will also trigg...

Страница 58: ...0x PLB master PLB_MErr will be asserted into the 60x PLB master by the targeted PLB slave on any 60x PLB transfer for which the responding PLB slave encounters an error In the CPC700 the only PLB slav...

Страница 59: ...to this error condition in various ways depending on how it is programmed See Section 5 10 3 7 PLB Master PLB_MErr Detection for details If ECC is enabled and an uncorrectable error is encountered for...

Страница 60: ...ister Description Processor interface registers are accessed through the PIFCFGADR and PIFCFGDATA registers To access one of the processor interface configuration registers write the appropriate index...

Страница 61: ...e 1 Enable 2 SNP60x_DIS 0 Disable snoop cycles on processor bus 0 All PLB accesses to system memory are snooped 1 All PLB accesses to system memory are snooped except those that fall within the range...

Страница 62: ...roller to generate an interrupt to the processor based on this condition or not See Section 3 16 17 PLBSWRINT PLB Slave Write Interrupt for information programming the PLB Slave Write Interrupt re gio...

Страница 63: ...Enabled This bit enables the detection of PLB Slave errors associated with transfers initiated by the 60x PLB Master Errors are asserted by a slave via the Merr signal 3 PLBM_LEN 0 PLB Master Lock Err...

Страница 64: ...transfer attributes for any errors associated with processor to memory transfers or processor transfers that generate an unsupported transfer type error 5 F_WR_ER_EN 0 Flash Write Error Enable 0 Detec...

Страница 65: ...ntire 16KB region programmed into the ending address register Example To program the internal PCI registers using a byte swapping region from xFEC0_0000 through FF40_3FFF program the following registe...

Страница 66: ...EA1 PLB Master Byte Swap Region 1 Ending Address PLBMTLEA1 contains the ending address of byte swapping region 1 This ending address identifies the ending of a byte swapping translation region with a...

Страница 67: ...PLBMTLEA2 PLB Master Byte Swap Region 2 Ending Address PLBMTLEA2 contains the ending address of byte swapping region 2 This ending address identifies the ending of a byte swapping translation region...

Страница 68: ...LEA3 PLB Master Byte Swap Region 3 Ending Address PLBMTLEA3 contains the ending address of byte swapping region 3 This ending address identifies the ending of a byte swapping translation region with a...

Страница 69: ...a 16KB granularity Address Offset x38 Width 32 Reset Value x0000_0000 Access Read Write 3 16 14 PLBSNSEA0 PLB Slave No Snoop Region End Address PLBSNSEA0 identifies the ending address of the no snoopi...

Страница 70: ...s available for test purposes only and allows error bits to be set A write access to x40 should provide a 32 bit mask where each 1 in the mask will clear the corresponding bit in the BESR A write acce...

Страница 71: ...m memory When the WR_INT_EN bit of the PRIFOPT1 regis ter is set a PCI to memory access hit in this 16KB region will generate an interrupt pulse one cycle in duration to the CPC700 interrupt controlle...

Страница 72: ...3 36 Processor Interface...

Страница 73: ...bank starting and ending addresses and memory addressing mode are all programmable During reset Bank 0 defaults to ROM and is enabled while all other banks are disabled Bank 0 is typically used for th...

Страница 74: ...the same system ECC checking may be disabled 4 2 Memory Controller Block Diagram A block diagram of the CPC700 memory controller is shown in Figure 8 Figure 8 Memory Controller Block Diagram Configur...

Страница 75: ...oller Configuration Address Register MEMCFGDATA FF50_000C R W Memory Controller Configuration Data Register Table 22 Offsets for Memory Controller Registers Register Offset R W Description MCOPT1 20 R...

Страница 76: ...cess if any is in progress A simple conceptual view of the priority associated with the routing of requests to the memory controller interface is shown in Figure 9 Figure 9 Routing of Memory Access Re...

Страница 77: ...to system memory from the local processor or PCI which address the same page within a given memory bank are treated as page hits provided that the addressed bank is active when the pipelined access re...

Страница 78: ...te Command SD_RTP Read to Pre charge Non Auto Precharge Mode The value programmed in this field should be determined empiri cally based upon the expected pattern of memory acceses If consecutive acces...

Страница 79: ...Auto Pre charge Enable Auto Precharge enable When enabled all SDRAM Read Write accesses will be performed as Read w Auto Precharge or Write w Auto Precharge SD_CASL CAS_ Latency Programmable access la...

Страница 80: ...f the SDRAM as follows ROW x COLUMN INTERNAL BANKS AP 1 if Auto Precharge is enabled AP 0 if Auto Precharge is disabled This bit field corresponds directly to SD_APGE from the SDTR1 configuration regi...

Страница 81: ...A21 A22 A23 A24 A25 A26 A27 A28 Mode 2 12 x 9 4 13 x 9 2 BA 1 BA 0 MA 12 MA 11 MA 10 AP MA 9 MA 8 MA 7 MA 6 MA 5 MA 4 MA 3 MA 2 MA 1 MA 0 Row A7 A8 A7 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 C...

Страница 82: ...11 MA 10 AP MA 9 MA 8 MA 7 MA 6 MA 5 MA 4 MA 3 MA 2 MA 1 MA 0 Row A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Column A6 A7 A7 A4 AP A5 A21 A22 A23 A24 A25 A26 A27 A28 Mode 3 13 x 11 4 BA...

Страница 83: ...5 A20 A21 A22 A23 A24 A25 A26 A27 A28 Mode 2 12 x 10 4 13 x 10 2 BA 1 BA 0 MA 12 MA 11 MA 10 AP MA 9 MA 8 MA 7 MA 6 MA 5 MA 4 MA 3 MA 2 MA 1 MA 0 Row A6 A7 A6 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18...

Страница 84: ...s are generated internally when the refresh timer expires The Refresh interval is program mable via the RTR register in the Global Memory Timing Registers During refresh all SDRAM and ROM accesses are...

Страница 85: ...t self refresh and wait a minimum of 12 clock cycles SD_SREX field of SDTR1 register before performing the access Once the SDRAM controller has exited self refresh mode it will not re enter self refre...

Страница 86: ...ing timing diagrams are included to illustrate the SDRAM programmable timing parameters only Figure 10 Mode Register Write Command 00000 01 0 010 SD_CASL CLOCK CKE BA 1 0 MA 12 MA 11 7 MA 6 5 MA 4 MA...

Страница 87: ...ge Figure 12 Write without Auto Precharge CLOCK CKE BA 1 0 MA 12 11 MA 10 AP MA 9 0 RAS_ SD_CS_ SD_RAS_ SD_CAS_ WE_ CAS_ SD_DQM DATA SD_RCD SD_RTP SD_CASL SD_PTA CLOCK CKE BA 1 0 MA 12 11 MA 10 AP MA...

Страница 88: ...recharge CLOCK CKE BA 1 0 MA 12 11 MA 10 AP MA 9 0 RAS_ SD_CS_ SD_RAS_ SD_CAS_ WE_ CAS_ SD_DQM DATA SD_RCD SD_RTP SD_PTA SD_CASL Auto Precharge Begins CLOCK CKE BA 1 0 MA 12 11 MA 10 AP MA 9 0 RAS_ SD...

Страница 89: ...Command Figure 16 CAS before RAS Refresh CLOCK CKE BA 1 0 MA 12 11 MA 10 AP MA 9 0 RAS_ SD_CS_ SD_RAS_ SD_CAS_ WE_ CAS_ SD_DQM SD_PTA CLOCK CKE BA 1 0 MA 12 0 RAS_ SD_CS_ 0 4 RAS_ SD_CS_ 1 5 RAS_ SD_C...

Страница 90: ...18 Memory Controller Figure 17 Self Refresh Entry Exit CLOCK CKE BA 1 0 MA 12 11 MA 10 AP MA 9 0 RAS_ SD_CS_ SD_RAS_ SD_CAS_ WE_ CAS_ SD_DQM SD_PTA SD_PTA Precharge all if necessary Self Refresh Exit...

Страница 91: ...CPC700 User s Manual Preliminary 4 19 4 5 9 2 CPU to Memory Timing Diagrams Figure 18 CPU Read Read 0 1 TS_ AACK_ DATA_ MA_ CS_ RAS_ RTRY_ CAS_ WE_ DQM DATA TA_ 2 3 4 5 6 7 0 1 2 3 4 5 6 7 U CLK...

Страница 92: ...4 20 Memory Controller Figure 19 CPU Read Write 0 1 TS_ AACK_ DATA_ MA_ CS_ RAS_ ARTRY_ CAS_ WE_ DQM DATA TA_ 2 3 4 5 6 7 0 1 2 3 CPU CLK...

Страница 93: ...CPC700 User s Manual Preliminary 4 21 Figure 20 CPU Write Read 0 1 TS_ AACK_ DATA_ MA_ CS_ RAS_ ARTRY_ CAS_ WE_ DQM DATA TA_ 2 3 4 5 6 7 4 5 6 7 CPU CLOCK...

Страница 94: ...4 22 Memory Controller Figure 21 CPU Write Write 0 1 TS_ AACK_ DATA_ MA_ CS_ RAS_ ARTRY_ CAS_ WE_ DQM DATA TA_ 2 3 0 1 2 3 4 5 6 7 CPU CLOCK...

Страница 95: ...DAck rd wr DBus PCI FRAME IRDY TRDY STOP AD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 Sync Read laten...

Страница 96: ...12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Write post buffer full Write Snoop Pre snoop Pre snoop Snoop PLB_CLK PCI_CLK BG TS AACK TA req addrAck rd wr Burst rd wr DAck rd wr DBus FRAME IR...

Страница 97: ...BG TS AACK TA req addrAck rd wr Burst rd wr DAck rd wr DBus FRAME IRDY TRDY STOP AD 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 Memory latenc...

Страница 98: ...12 Read line Snoop Snoop PLB_CLK PCI_CLK BG TS AACK TA req addrAck rd wr Burst rd wr DAck rd wr DBus FRAME IRDY TRDY STOP AD 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 11 10 9 8 7 6 5 4 3 2 1 Write Delay...

Страница 99: ...CPU Line Read PCI Burst Read 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Line Read Snoop PLB_CLK PCI_CLK BG TS AACK TA req addrAck rd wr Burst rd wr DAck rd wr DBus FRAME IRDY TRDY STOP AD 14 13 12 11 10 9 8 7 6...

Страница 100: ...ller Figure 27 CPU Line Read to PCI Write Burst 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Write Snoop PLB_CLK PCI_CLK BG TS AACK TA req addrAck rd wr Burst rd wr DAck rd wr DBus FRAME IRDY TRDY STOP AD CPU PLB...

Страница 101: ...Chip select signals are generated when the CPC700 detects accesses to addresses bracketed by the contents of a memory bank starting ending address register pair MBxSA MBxEA The comparison of address...

Страница 102: ...equential single byte reads from the ROM device starting on the doubleword boundary and the entire assembled doubleword will be returned to the processor Care must be taken when attaching peripherals...

Страница 103: ...dress 5 6 7 8 12 373 Latch 23 6 7 8 9 11 22 7 8 9 10 9 21 8 9 10 11 8 20 9 10 11 12 7 19 10 11 12 13 6 18 11 12 13 14 5 17 12 13 14 15 4 16 13 14 15 16 3 15 14 15 16 17 2 14 15 16 17 18 1 13 16 17 18...

Страница 104: ...is shared with the DRAM SDRAM controller A complete list of registers affecting ROM operation follows Detailed descriptions of these registers can be found in Section 4 9 Memory Controller Register De...

Страница 105: ...hment as this bit is also used as the Auto Precharge AP bit for SDRAM The CPC700 is inherently a Big Endian system ROM and peripherals which are typically specified as litttle endian should be connect...

Страница 106: ...MA READ WRITE RNW CS OE WE W_DATA R_DATA 3 5 6 7 8 9 10 11 12 4 1 2 0 3 CSON 0 3 OEON 0 3 WEON OEON 0 3 1 TWT THDRD THDWR WEOFF Data Sampled On READS 0 1 Clock ALE MA READ WRITE RNW CS OE R_DATA 1 FW...

Страница 107: ...CPC700 User s Manual Preliminary 4 35 Figure 31 Non Burst Read Figure 32 Single Write Synchronous Ready Enabled clock ALE MA READ WRITE RNW CS OE R_DATA clock ALE MA READ WRITE RNW CS WE W_DATA READY...

Страница 108: ...ry Controller Figure 33 Single Write Asynchronous Ready Enabled Figure 34 Non Burst Read Synchronous Ready Enabled clock ALE MA READ WRITE RNW CS WE W_DATA READY clock ALE MA READ WRITE RNW CS OE R_DA...

Страница 109: ...al Preliminary 4 37 Figure 35 Non Burst Read Synchronous Ready Enabled Figure 36 Burst Mode Read Asynchronous Ready Enabled clock ALE MA READ WRITE RNW CS OE R_DATA READY clock ALE MA READ WRITE RNW C...

Страница 110: ...rd SEC DEC coverage The ECC module corrects all single bit errors and detects all double bit errors when reading from memory including the case where a single bit data and single bit address er ror oc...

Страница 111: ...width due to the use of the single DQM in this situation Partial writes will result in read modify write cycles to the non ECC memory banks Systems which do not require ECC protection may configure th...

Страница 112: ...ic bank is disabled the Correction Enable for that bank is a don t care This setting is used for ROM 1 1 0 ECC globally enabled If a specific bank is enabled for ECC and dis abled for correction check...

Страница 113: ...t of ECC is as follows 1 immediately following reset the ECC logic is disabled by default 2 configure and enable the memory ROM controller using DCR cycles 3 write to system memory 4 read from memory...

Страница 114: ...8 DH2 A 29 0 A 30 31 10 16 23 A 2 0 A 1 0 10 0100 23 16 DH3 A 29 0 A 30 31 11 24 31 A 2 0 A 1 0 11 1000 31 24 DL0 A 29 1 A 30 31 00 32 39 A 2 1 A 1 0 00 0001 7 0 DL1 A 29 1 A 30 31 01 40 47 A 2 1 A 1...

Страница 115: ...med Note In the tables of register field descriptions throughout this specification some bits are shown shaded Those bits are reserved in the CPC700 Reading of reserved bits will produce unpredictable...

Страница 116: ...this time the timing parameters for the respective controller should be configured Once enabled SDRAM will be initialized via the power on sequence and subsequently avail able for access 1 SLFREFEN 0...

Страница 117: ...3 MEMTYPE Installed Memory Type Address Offset x28 Width 32 Reset Value x0000_0000 Access Read Write This register must be configured for each memory bank that is enabled Bit Name Reset Value Descript...

Страница 118: ...0 Memory 00 ROM 01 DRAM 1x RESERVED These bits default to 00 to enable boot ROM in bank 0 2 3 MT_1 0 Bank 1 Memory 00 ROM 01 DRAM 1x RESERVED 4 5 MT_2 0 Bank 2 Memory 00 ROM 01 DRAM 1x RESERVED 6 7 M...

Страница 119: ...egisters contain the starting addresses for banks 1 through 4 The minimum granularity for installed memory is 1M Byte 4 9 1 7 MBxEA Memory Bank 1 4 Ending Address Address Offset x5C 60 64 68 Width 32...

Страница 120: ...rved Bit Name Reset Value Description 0 6 0s Reserved 7 8 SD_CASL 00 SDRAM CAS_ latency 00 2 CLK 01 3 CLK 1x Reserved This setting is used during the SDRAM Mode Set Command 9 SD_APGE 0 SDRAM Auto Prec...

Страница 121: ...harge latency 0000 Reserved 0001 1111 Binary Decode 1 15 Clocks 18 21 SD_RTP 0111 SDRAM Read Command to Precharge Command minimum SDRAM Read with Auto Precharge Command to Auto Pre charge latency 0000...

Страница 122: ...ss Read Write The 16 bit field of this register determines the memory refresh rate for SDRAM The internal counter runs at the processor bus frequency thus at 66 MHz 15ns cycle time a value of 0x03F8 1...

Страница 123: ...ory Mapping for information on the var ious addressing modes available Bit Name Reset Value Description 0 1 DAM_0 0s Bank 0 Addressing mode 00 Mode 1 01 Mode 2 10 Mode 3 11 Mode 4 2 3 DAM_1 0s Bank 1...

Страница 124: ...sfers The number of cycles from address valid to the deassertion of CS_ is 1 TWT NWT Next Wait Burst Mode Enabled BME 1 6 7 CSON 00 Chip Select On Timing Measured with respect to Address Valid 00 CS_...

Страница 125: ...RE 0 Ready Enable 0 Device pacing via Ready input is Disabled 1 Device pacing via Ready input is Enabled 22 ARE 0 Asynchronous ready Enabled Ready Enabled RE 1 0 Ready input is synchronous Data Sample...

Страница 126: ...00 8 bit 01 16 bit 10 32 bit 11 64 bit Reset value determined by strapping option See Section 6 4 Power on Reset Pin Strapping Options Strapping Pins Bit 0 TT 0 Processor bus Transfer Type Bit 1 TT 1...

Страница 127: ...s read write capable A write attempted to a bank whose FLSHWEN bit is disabled will result in a memory select error Bit Name Reset Value Description 0 FLSHWEN_0 0 Bank 0 Flash write enable 0 Disable 1...

Страница 128: ...dth 1 32 bit Width 5 7 0 Reserved 8 ECC_BANK0_EN 0 ECC Bank 0 Enable 0 Bank Disabled 1 Bank Enabled If ECC is globally enabled bit 1 1 these bits 8 16 control how the ECC controller will perform memor...

Страница 129: ...n_Enable bit is set to zero When a CORRECTIONn_Enable bit is set to one ECC correction will be enabled When it is set to zero ECC will ignore the checkbits and pass the data along unmodified 17 ECC_BA...

Страница 130: ...erate an interrupt to the processor based on this condition or not See Section Chapter 10 Interrupt Controller for more information Bit Name Reset Value Description 0 B0CE 0 Byte Lane 0 Corrected Erro...

Страница 131: ...0 CE 0 Correctable Error 11 UE 0 Uncorrectable Error 12 AP 0 Address Parity Error 13 15 0 Reserved 16 BNK0ERR 0 Bank 0 Error 0 No Error 1 Error Occurred in Bank 0 17 BNK1ERR 0 Bank 1 Error 0 No Error...

Страница 132: ...4 60 Memory Controller...

Страница 133: ...ress spaces Single beat PCI I O reads and writes PCI memory single beat and prefetch burst reads and single beat writes Single beat PCI configuration reads and writes type 0 and type 1 PCI interrupt a...

Страница 134: ...k diagram is shown in Figure 38 Figure 38 PCI Interface Macro Block Diagram PLB Slave PLB Master Reg Block CONFIG PCI Master I F PLB Slave I F Bus Bus W B R B PCI Target I F W B R B PLB Master I F Int...

Страница 135: ...MM0PCILA FF40_0008 R W PMM 0 PCI Low Address PMM0PCIHA FF40_000C R W PMM 0 PCI High Address PMM1LA FF40_0010 R W PMM 1 Local Address PMM1MA FF40_0014 R W PMM 1 Mask Attribute PMM1PCILA FF40_0018 R W P...

Страница 136: ...1 BAR PCIPTM2BAR 18 R W PTM 2 BAR Reserved 1C 27 Unused BARs Reserved 28 2B Unused Cardbus PCISUBSYSID 2C R W PCI Subsystem ID PCISUBSYSVENDID 2E R W PCI Subsystem Vendor ID Reserved 30 3B Unused or...

Страница 137: ...pecial Cycle hFED0_0004 hFEDF_FFFF Reserved hFEE0_0000 hFF3F_FFFF Reserved PCI Macro does not respond hFF40_0000 hFF4F_FFFF PCI interface Local Configuration Registers hFF40_0000 PMM 0 Local Address h...

Страница 138: ...ch PMM is also programmable and is a 64 bit address This allows address translation between the two busses The least significant word of the PCI address is defined in the PCI Low Address registers The...

Страница 139: ...trolled by the registers PTM 2 Memory Size Attribute Local Config register PTM 2 Local Address Local Config register PTM 2 BAR PCI Config register 18 The location in PCI Memory space of each PTM is pr...

Страница 140: ...interface generates PLB transactions based on the type and length of PCI transactions received The following sections describe the transaction types supported and outline the translation of commands...

Страница 141: ...while there are PCI master writes posted a delayed read is initiated These posted writes are completed on the PLB bus before the read is run The PCI interface continues to accept post PCI master writ...

Страница 142: ...don t cares for PCI reads The PCI interface performs word burst or single beat reads on the PLB regardless of the byte enables presented by the requesting PCI master Note this rule assumes that all P...

Страница 143: ...will be at most 3 bytes because that is the maximum size possible for a PCI data phase with contiguous but not all active byte enables Example A PCI master device executes an 8 beat write The active...

Страница 144: ...ingle beat write 1 4 byte2 PCI complete transaction post PLB request bus PLB_M x AddrAck of posted write request transfer data to PLB memory write sin gle beat single beat write 1 4 byte2 PCI complete...

Страница 145: ...that decode to the CONFIG_DATA register Memory Read This command is generated in response to PLB 1 4 byte reads that decode to one of the three PMMs when the PMM is marked as non prefetchable Memory...

Страница 146: ...e is rearbitrated When the PCI interface receives PLB 1 4 byte read requests that decode to a PMM marked as prefetch able the PCI interface burst reads up to 64 bytes from the PCI and saves the data i...

Страница 147: ...es CPU to PCI Transactions Table 44 describes the PCI interface s response to PLB master requests The PCI terms retry and dis connect refer to respectively transaction abort with no data transferred a...

Страница 148: ...ith Sl x _MErr write 1 4 byte memory I O PLB complete transaction post if buffer available PCI request bus retry or discon nect re request PCI bus write 1 4 byte memory I O PLB complete transaction po...

Страница 149: ...at all 5 8 2 Completion Ordering The CPC700 implements the following completion ordering rules 1 PCI master writes are accepted if there is room in the PCI write post buffer 2 New PCI master reads are...

Страница 150: ...ating frequencies through the use of strapping pins where pullup or pulldown resistors on certain CPC700 I O signals are read during system reset The strapping pins and the corresponding frequency mod...

Страница 151: ...ccurs In asynchronous mode one wait state is added after about every fourth transfer as long as FIFO is not full thus maximum bandwidth is reduced about 20 Also disconnects occur more frequently PCI m...

Страница 152: ...ed addresses in PLB space They must be accessed using single beat read or write cycles of the same size as shown in the register descriptions below Failure to access all bytes of a particular register...

Страница 153: ...dress FF40_000Ch Width 32 bits Reset Value Undefined Table 47 PMM 0 Mask Attribute Register Bits Bit s Name Description 0 Enable This bit determines if range 0 is enabled to map PLB space to PCI Mem o...

Страница 154: ...ce that is mapped to PCI Memory See PMM 0 Local Address for details 5 9 1 6 PMM 1 Mask Attribute PLB Address FF40_0014h Width 32 bits Reset Value 0000_0000 Access Read Write This register defines the...

Страница 155: ...Reset Value 0000_0000 Access Read Write This register defines the size and attributes of range 2 in PLB space that is mapped to PCI Memory See PPMM 0 Mask Attribute for details 5 9 1 11 PMM 2 PCI Low...

Страница 156: ...other least significant bits of the PLB address are passed through from the PCI address Only bits 31 12 are writable bits 11 0 are always zero 5 9 1 15 PTM 2 Memory Size Attribute PLB Address FF40_00...

Страница 157: ...t addresses FEC0_0000 and FEC0_0004 instead of CF8h and CFCh and are named PCICFGADR and PCICFGDATA instead of CONFIG_ADDRESS and CONFIG_DATA PCICFGADR and PCICFGDATA should be accessed with single be...

Страница 158: ...Bus Number is ZERO and the Device Number is greater than ZERO During the address phase of the configuration cycle AD11 is asserted if the Device Number is 1 AD12 is asserted if the Device Number is 2...

Страница 159: ...the new value and writing the result NOTE All registers are represented in Little Endian notation i e the most significant byte corresponds to the highest address 5 9 3 1 PCI Vendor ID Register Addre...

Страница 160: ...bles special palette snooping The CPC700 is not a VGA device therefore this bit is read only and returns 0 when read 6 Parity Error Response Parity error response This bit enables the detection of all...

Страница 161: ...items therefore this bit is read only and returns 0 when read 7 Fast Back to Back Capable Indicates that the PCI target is capable of accepting fast back to back transactions when the transactions are...

Страница 162: ...d Master Abort This bit is set whenever the CPC700 terminates a PCI cycle for which it is the master with master abort Writing a 1 to this bit resets it to 0 14 Signaled System Error Signaled system e...

Страница 163: ...eturns 00h when read 5 9 3 8 PCI Latency Timer Address Offset 0Dh Width 8 Reset Value 07h Access Read Write The PCI latency timer register is an 8 bit read write register used to hold the value of the...

Страница 164: ...ess Register 1 PCIPTM1BAR Address offset 14h Width 32 bits Reset Value 0000_0008h Access Read Write This register defines a space in PCI Memory space that is mapped to PLB space system memory or ROM F...

Страница 165: ...ways ZERO 5 9 3 15 PCI Cardbus CIS Pointer Unused Address offset 28h 2Bh Unused and always ZERO 5 9 3 16 PCI Subsystem ID Register Address Offset 2Ch Width 16 Reset Value 00h Access Local Read Write P...

Страница 166: ...offset 3Ch Width 8 Reset Value 00h Access Read The PCI interrupt line register is used to communicate interrupt line routing information The CPC700 does not implement an interrupt pin therefore this...

Страница 167: ...ontrolled by the CPC700 The CPC700 is not a PCI to PCI bridge therefore this register is read only and returns 00h when read 5 9 3 24 PCI Subordinate Bus Number Address offset 41h Width 8 Reset Value...

Страница 168: ...eans request 0 has the highest priority while request 5 has the lowest Bus parking modes and max transfer counts per grant can be pro grammed via the PCI Arbiter Control register Figure 42 Arbiter Pri...

Страница 169: ...s bit enables the assertion of Sl x _MErr when the PCI interface is a PLB slave A value of 1 enables Sl x _MErr assertion A value of 0 disables Sl x _MErr assertion 3 MErr Detection Enable This bit en...

Страница 170: ...PCI interface decodes the PCI interface allows such requests to timeout 1 PCI_SERR on Write Data Parity Error This bit is set when the CPC700 drives PCI_SERR PCI_PERR is also driven in response to a d...

Страница 171: ...aster is zero PLB_lockerr is driven high to the PCI interface s PLB slave and an error associated with that master occurs the error will be reported and the MxFL field will be set Subsequent errors wi...

Страница 172: ...ock 0 SESR Unlocked 1 SESR Locked 22 M1RWS Master 1 the PCI interface in the CPC700 Read Write Status 0 Error operation was a Write 1 Error operation was a Read 25 23 M1ET Master 1 the PCI interface i...

Страница 173: ...SEAR1 Address offset 57h 54h Width 32 Reset Value 0000h Access Read The PLB Slave Error Address register 1 contains the address associated with an error on the PLB bus as indicated by the PLB slave a...

Страница 174: ...itialize them before the Host sees them 1 Reserved When 1 this bit disables the PCI Target latency timer This pre vents the use of the Delayed Read mechanism 2 PCI Discard Timer Disable When 1 the CPC...

Страница 175: ...done All errors are associated with either a cycle on the PLB bus or a cycle on the PCI bus Each error that can be detected has a mask associated with is If the mask is set then the detection of that...

Страница 176: ...onously to the actual corresponding write data beat on the PLB For connected writes Sl x _MErr will be asserted with the data transfer and the data will be discarded If Master Abort Error Enable is cl...

Страница 177: ...2 If a target abort is detected as an error register 49h bit 2 Error Status Register MErr Assertion Event bit is set to indicate an event which would cause Sl x _MErr to be asserted by the bridge PLB...

Страница 178: ...f the state of the Parity Error Response bit The Parity Error Detected bit can be cleared by writing a 1 to it 2 If a data bus parity error is detected as an error register 49h bit 2 Error Status Regi...

Страница 179: ...er PCI_SERR Asserted bit is set Setting of the PCI_SERR Asserted bit is non maskable It can be reset by writing a 1 to it 3 If the CPC700 PCI target asserts PCI_SERR register 49h bit 4 Error Status Re...

Страница 180: ...nding as a PCI memory target is allowed 5 11 1 2 Example Address Map Setup Figure 43 shows the desired address map System memory resides from 0 to 0FFF_FFFFh in the CPU PLB address space It is accessi...

Страница 181: ...9 Figure 43 Example Address Map ROM Memory CPU PLB PCI Memory Space PMM1 PMM0 PTM1 BAR1 Prefetchable PCI Targets Non Prefetchable PCI Targets 8C00_0000 8800_0000 8000_0000 1000_0000 9400_0000 9000_000...

Страница 182: ...Error Enable register must be initialized appropriately The PCI arbiter defaults are enabled Arbiter options are programmable via the PCI Arbiter Control reg ister If an external arbiter is used the...

Страница 183: ...the following registers if the default value is not suitable before setting the Host Config Enable bit The address map see Section 5 11 1 1 Address Map Initialization PCI Vendor ID PCI Device ID PCI...

Страница 184: ...5 52 PCI Interface...

Страница 185: ...HRESET logic The CPC700 internal latches will be reset at the same time as if a System Reset had occurred with the exception that the PLL tuning bits will retain the values just written to them Drivi...

Страница 186: ...events at power on are as follows 1 System activates SYS_RESET_N active low to the CPC700 2 CPR holds reset active to the two internal PLLs for the entire time that SYS_RESET_N is active This ensures...

Страница 187: ...ower supply supervisor power on reset etc drive an active low signal into the SYS_RESET_N input of the CPC700 The CPC700 activates the RESET_OUT_N signal from the asser tion of SYS_RESET_N until 500 s...

Страница 188: ...now one of the sources driving HRESET to the CPU 6 3 2 Internal Peripheral Reset Control In addition to being reset with the system reset SYS_RESET_N the individual internal peripherals may each be r...

Страница 189: ...Enable PLL pulldown Bypass PLL pullup Shared DQM ECC Enable DQM 1 7 pullup Enable ECC 1 7 pulldown Table 63 PCI Frequency Modes CPC700 I O Clocking Mode PCI Frequency Range TSIZ 1 TSIZ 2 PCI_66_STR AP...

Страница 190: ...UART IIC and GPT internal peripherals Note that setting a peripheral s reset bit in the CPRRESET register will hold the peripheral in a reset state until its reset bit is cleared written to a logic 0...

Страница 191: ...ered When enabled in the CPC700 s interrupt controller these events can be used to interrupt the processor Table 65 Peripheral Reset Control Register Bit Name Default Description 0 UART0_RST 0 UART 0...

Страница 192: ...SET_OUT_N See Section 6 1 1 PLL Tuning for important information regarding this register Note If changes from the default values are required contact your IBM representative for proper values for this...

Страница 193: ...Asynchronous PCI Mode 0 PCI Frequency 50MHz 1 PCI Frequency 50MHz In Synchronous PCI Mode This bit is a Don t Care 1 PCIFREQ1 Pin PCI_66_STRAP 0 PCI Frequency Select 1 0 PCI Frequency 25 35MHz 1 PCI F...

Страница 194: ...6 10 Clock Power Management and Reset...

Страница 195: ...nterrupt This UART is functionally identical to NS16550 in character mode on power up it will be in this mode and can be put into FIFO mode to relieve the processor of excessive software overhead Here...

Страница 196: ...dently controlled transmit receive line status and data set interrupts Programmable baud rate generator divides the UART serial clock input by 1 to 216 1 and generates the 16x clock Baud rate bits s C...

Страница 197: ...Register UARTxFCR FF60_0X02 W UART x FIFO Control Register UARTxLCR FF60_0X03 R W UART x Line Control Register UARTxMCR FF60_0X04 R W reserved UARTxLSR FF60_0X05 R W UART x Line Status Register UARTx...

Страница 198: ...valid bit of the MCR in this two wire implementation of the UART is MCR bit 4 the Loopback Mode bit which can be used for diagnostic purposes Note Register bit definitions are shown in big endian not...

Страница 199: ...Even Parity Select Bit When bit 3 is a logic 1 an odd number of logic 1 s is transmitted or checked in the data word and the parity bits 1 Even Parity Select Bit When bit 4 is a logic 1 an even numbe...

Страница 200: ...CPC700 interrupt controller This bit is set to logic 1 when a character is transferred from the THR to the transmitter shift register In FIFO mode this bit is set when the transmitter FIFO is empty 3...

Страница 201: ...receiver FIFO or the receiver buffer register 1 Receiver data ready DR indicator An entire incoming character has been received into the RBR or receiver FIFO Table 74 FIFO Control Register Descriptio...

Страница 202: ...e 1 that is written into this position is self clearing 1 Receiver FIFO reset A logic 1 written here will clear all bytes in the receiver FIFO and reset all of its counter logic to 0 The receiver shif...

Страница 203: ...evel Interrupt Type Interrupt Source Interrupt Reset Control 0 1 1 1st Receiver Line Status Overrun Parity or Framing Error or Break Interrupt Read LSR 0 1 0 2nd Received Data Available Receiver data...

Страница 204: ...9600 54 rounded 0x36 For this example the Divisor Latch MSB register should be programmed to 0 and Divisor Latch LSB regis ter should be programmed to 0x36 Due to the error introduced by rounding some...

Страница 205: ...FIFO timeout will occur when At least one character is in the receiver FIFO no serial characters have been received for four serial character time periods and the processor has not read the FIFO for f...

Страница 206: ...nd or transmitter Bits 3 6 of the LSR specifies which errors if any have occurred Character status errors are handled in the same way as in interrupt mode Since bit 5 of the IER 0 the IIR is not affec...

Страница 207: ...ced features of the Philips Semiconductors I2 C Specification 100 and 400 kHz operation 8 bit data transfers 7 bit and 10 bit address decode generation Slave transmitter and receiver Master transmitte...

Страница 208: ...C interface is performing a read operation Table 78 IIC Registers Facility Name Mnemonic CPC700 Map Addres s hex Type Affected by Reset Size bits Master Data Buffer IICxMDBUF FF6X_0000 0x0 R W Yes cle...

Страница 209: ...he interrupt mask register is used to control which interrupts can be issued The transfer count register is used to indicate the number of bytes actually transferred across the IIC bus in a master or...

Страница 210: ...r on the IIC bus This allows the overlapping of slave and master transfer operations The bit assignments for the master data buffer and the slave data buffer are identical Care must be taken not to st...

Страница 211: ...ompleted The remaining bits are left unaffected Count bits 0 1 bits 2 3 of the Control Register are defined as follows 0x0 Transfer one byte 0x1 Transfer two bytes 0x2 Transfer three bytes 0x3 Transfe...

Страница 212: ...bus bit 5 Chain When set to a logic 1 the requested master transfer is one in a sequence of transfers Completion of the requested transfer only indicates that this piece of the transfer is complete T...

Страница 213: ...f the read operation or that the slave data buffer has gone empty during the read operation How the IIC interface handles not ready conditions can potentially affect system performance A slave that ho...

Страница 214: ...he third system clock after the transfer For byte accesses the status will be readable on the second system clock after the transfer Bits 0 2 3 5 and 7 are read only bit 6 Exit unknown IIC bus state W...

Страница 215: ...re The pending and on deck interrupts along with the active interrupt in the status register form a miniature FIFO for storing the interrupts A new interrupt is first set into the pending state It wil...

Страница 216: ...ted This bit might also be momentarily set while a new interrupting condition moves from the on deck to the active state When IRQ active is set to a logic 0 an on deck IRQ will cause IRQ active to be...

Страница 217: ...IIC bus Since the base clock is used as the basis for all setup and hold timings on the IIC bus it is imperative that the correct value is used If the wrong value is used the IIC interface will violat...

Страница 218: ...is received during a read the slave read complete bit bit 0 of the extended control and slave status register is also set to a logic 1 bit 1 Enable IRQ on slave read needs service The interrupt is act...

Страница 219: ...equent to setting bit 7 to a logic 0 a minimum of eight system clock periods must occur before any other registers in the IIC interface are programmed Care must be used when changing the setting of bi...

Страница 220: ...n the IIC bus is being held busy until slave read needs service is cleared to a logic 0 Also in this first case if enable hold SCL is set to a logic 0 then a not acknowledge is sent to end the current...

Страница 221: ...becomes the on deck interrupt Any status associated with one of the multiple interrupts is immediately set into its corresponding register Thus it is possible for an interrupt service routine to see t...

Страница 222: ...to send one byte of data out over the IIC interface One of the first things that should be done by the program is to write the byte that is to be sent into the buffer If the program wanted to check th...

Страница 223: ...t must be avoided are those which are listed in the Phillips Semiconductors I2 C Specification dated 1995 Section 7 2 For your convenience the section is summarized as fol lows If multiple masters can...

Страница 224: ...8 18 IIC...

Страница 225: ...d via load store instructions using the addresses shown in Table 96 Table 96 GPT Registers Base Address Register Register Name Access Mode Width bits FF65_0000 GPTTBC GPT Time Base Counter R W 32 FF65...

Страница 226: ...t its maximum value all bits set to 1 it will roll back to zero upon the next clock The TBC may be read and written by software using its memory mapped address The TBC is synchronously reset to zero u...

Страница 227: ...he CPC700 The bits in the CPRCAPTEVNT register can be made falling edge active set to 0 to trigger or rising edge active set to 1 to trigger via the GPT Edge Detection Control GPTEC register Refer to...

Страница 228: ...d when all bits either com pare or are masked the GPT Interrupt Status GPTIS Register bit is set indicating a valid comparison Further if the corresponding GPT Interrupt Enable GPTIE Register bit is s...

Страница 229: ...with the GPT_RST bit in the CPRRESET register To save on power consumption only those registers required to bring the GPT to a stable state are reset with GPT_RST Other registers should be programmed...

Страница 230: ...tware to use as a general timer All TBC bits reset to zero 0 9 3 2 GPT Capture Enable GPTCE Register Figure 50 Capture Timers Enable Register Bits 0 4 map to the corresponding capture timer and bits 5...

Страница 231: ...nt signal as defined in the CPR CAPTEVNT register see Figure 52 Bits 5 31 are reserved When zero 0 the non synchronized path is selected and when one 1 the synchronized path is selected Using the sync...

Страница 232: ...us and the lower half bits 16 20 correspond to the compare timer interrupt status see Figure 54 GPTIS status bits for the capture timers are set when a capture event occurs the capture timer is enable...

Страница 233: ...re Timer Register captures the value of the TBC whenever its corresponding capture event is triggered and its capture timer is enabled The width of each Capture Timer Register is 32 bits All Capture T...

Страница 234: ...ure Event Generation Register This register is provided to signal events that will cause the capture timers to trigger System software may set and reset these bits as desired to time certain system ev...

Страница 235: ...ocal memory range interrupt ECC correctable error interrupt Interrupts are individually maskable Interrupts can be individually programmed to generate a machine check exception MCP or an exter nal int...

Страница 236: ...es were placed in sequential memory locations allowing 512 0x200 bytes for each then with the proper base address the vector generated by the UIC could point directly to the interrupt service routine...

Страница 237: ...considered the highest priority From whatever end of the Status reg ister that is considered highest priority the next bit is the next in priority and so on to the lowest priority at the opposite end...

Страница 238: ...r an external interrupt to the processor MCP pro grammed interrupts when properly enabled and when the MCP enable bit bit 1 of the PRIFOPT1 register is set will drive the CPC700 s MCP_N output signal...

Страница 239: ...on 10 5 2 UICSRS UIC Status Register Set Figure 57 UICSRS UIC Status Register Set Register Address R W Description UICSR FF50_0880 R C UIC Status Register Read Clear UICSRS FF50_0884 R S UIC Status Re...

Страница 240: ...UICCR UIC Critical Register Figure 59 UICCR UIC Critical Interrupt Register The bits of the UICCR correspond one to one with the bits of the UICSR Each bit in the UICCR is used to determine whether an...

Страница 241: ...on how to program the edge level trigger register for the CPC700 10 5 6 UICTR UIC Trigger Register Figure 61 UICTR UIC Trigger Register The bits in the UICTR will be used to program the interrupt inpu...

Страница 242: ...pt handler routines associated with each interrupt The vector base address set in the UICVCR is used when calculating the interrupt vector The two least significant bits of this address are always ass...

Страница 243: ...ken When using this method the interrupt service routines should be placed 512 0x200 bytes apart The interrupt vector is generated for the highest priority interrupt which is currently enabled active...

Страница 244: ...10 10 Interrupt Controller...

Страница 245: ...ell as for the support of board level testing and debug The following JTAG commands are supported by the CPC700 JTAG TAP controller 1 EXTEST 2 SAMPLE PRELOAD 3 BYPASS 4 CLAMP 5 IDCODE 6 USERCODE The C...

Страница 246: ...I 11 2 JTAG...

Страница 247: ...PLB priority level and thus its priority level cannot be changed The default PLB priority level of the PCI PLB Master is also the highest but it can be changed by software A register associated with...

Страница 248: ...master Once locked the PEAR cannot be updated if a subsequent error occurs until all PESR FLCKn fields are cleared n is the master ID Table 102 PLB Arbiter Registers Mnemonic Register Name Address Ac...

Страница 249: ...he 60x PLB processor interface 1 R W0 Master 0 Read Write Status 0 Master 0 error operation was a write 1 Master 0 ICU error operation was a read 2 FLK0 Master 0 PESR Field Lock 0 Master 0 PESR field...

Страница 250: ...12 4 Processor Local Bus PLB...

Страница 251: ...GESR GESR fields can be locked using the GESR FLKn and GESR ALKn fields n is the master ID Once locked the GESR fields associated with a master cannot be overwritten if a subsequent error occurs until...

Страница 252: ...s locked 5 6 PTE1 PLB Timeout Error Status Master 1 00 No master 1 error occurred 01 Master 1 timeout error occurred 10 Master 1 slave error occurred 11 Reserved Master 1 is the PCI interface 7 R W1 R...

Страница 253: ...16 Processor Interface Register Description for detailed register information Table 102 Processor Interface Register Addressing Register Address R W Description PIFCFGADR FF50_0000 R W Processor Inte...

Страница 254: ...ite Interrupt Region Base Address Table 104 Memory Controller Register Addressing Register Address R W Description MEMCFGADR FF50_0008 R W Memory Controller Configuration Address Register MEMCFGDATA F...

Страница 255: ...4 R W ROM Peripheral Bank 1 Parameters RPB2P E8 R W ROM Peripheral Bank 2 Parameters RPB3P EC R W ROM Peripheral Bank 3 Parameters RPB4P F0 R W ROM Peripheral Bank 4 Parameters Table 106 PCI Interface...

Страница 256: ...FEC0_0004 R W PCI Configuration Data Register Table 107 PCI Configuration Register Offsets PCI Config Register Offset R W Description PCIVENDID 01 00 R W Vendor ID PCIDEVID 03 02 R Device ID PCICMD 0...

Страница 257: ...1 60 R W Bridge Options 2 Table 108 Clock Power Management and Reset Control Registers Register Address R W Description CPRPMCTRL FF50_0900 R W Peripheral Power Management Control CPRRESET FF50_0904 R...

Страница 258: ...egister Address R W Description UICSR FF50_0880 R C UIC Status Register Read Clear UICSRS FF50_0884 R S UIC Status Register Set UICER FF50_0888 R W UIC Enable Register UICCR FF50_088C R W UIC Critical...

Страница 259: ...gister Address R W Description IIC1MDBUF FF63_0000 R W IIC1 Master Data Buffer Reserved FF63_0001 IIC1SDBUF FF63_0002 R W IIC1 Slave Data Buffer Reserved FF63_0003 IIC1LMADR FF63_0004 R W IIC1 Low Mas...

Страница 260: ...Register UART0LSR FF60_0305 R W UART 0 Line Status Register UART0MSR FF60_0306 R W UART 0 Modem Status Register UART0SCR FF60_0307 R W UART 0 Scratch Register UART0DLL FF60_0300 R W UART 0 Divisor Lat...

Страница 261: ...PTIS FF65_0020 R Timers Interrupt Status Clear upon Read GPTIE FF65_0024 R W Timers Interrupt Enable Reserved 28 3C GPTCAPT0 FF65_0040 R Capture Timer 0 GPTCAPT1 FF65_0044 R Capture Timer 1 GPTCAPT2 F...

Страница 262: ...14 10 Register Summary...

Страница 263: ...7 TBST_N R19 I O LVTTL 11 7 3 3 TSIZ0 P16 I O LVTTL 11 7 pd 13K 3 3 TSIZ1 N13 I O LVTTL 11 7 pd 13K 3 3 TSIZ2 N11 I O LVTTL 11 7 pu 20K 3 3 TS_N P14 I O LVTTL 11 7 3 3 TT0 R15 I O LVTTL 11 7 pd 13K 3...

Страница 264: ...O PCI note 1 note 1 PCI_SERR_N M06 I O PCI note 1 note 1 5 0 PCI_STOP_N T04 I O PCI note 1 note 1 5 0 PCI_TRDY_N P06 I O PCI note 1 note 1 5 0 ROM_ALE H14 O LVTTL 11 7 ROM_OE_N K12 O LVTTL 12 18 ROM_...

Страница 265: ...tatus register 7 6 M Memory Access Arbiter 4 4 Memory Controller 4 1 Memory Interface Singals 2 5 O Overview 1 1 P PACR 12 2 Page Mode Access 4 5 parallel to serial conversion 1 8 7 1 PCI Bus Interfac...

Страница 266: ...al interface characteristic 7 2 serial to parallel conversion 1 8 7 1 Signal Descriptions 2 1 Snoop Cycles 3 12 SPCTL 9 6 SPHS 9 6 SPLS 9 9 SPRB 9 9 SPRC 9 7 10 5 10 6 10 7 10 8 10 9 SPTB 9 7 System I...

Страница 267: ...CPC700 User s Manual Preliminary...

Страница 268: ...tion contained herein Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties The products described in this...

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