IBM CPC700, Руководство пользователя

Страница: 124 / 268

4-52 Memory Controller
4.9.3 ROM Specific Configuration Registers
4.9.3.1 RPBxP - ROM/Peripheral Bank Parameters
Address Offset: xE0, E4, E8, EC, F0
Width:
32
Reset Value: xFC03_F8F0
Access: Read/Write
These configuration registers consist of one register per bank with each register being used to
configure the access modes and timings on a per-bank basis. The controller has programmable
timings that allow for ROM, SRAM, and peripheral support. An external READY input is provided
to allow for device-paced transfers on both READs and WRITEs. When enabled, READY input
may be configured to be either synchronous or asynchronous.
.
Bit
Name Reset
Value Description
0:5 TWT x3F Transfer Wait (Burst Mode Disabled: BME=0)
Wait states on all non-burst transfers.
The number of cycles from address valid to the deassertion of
CS_ is 1+TWT.
NWT Next Wait (Burst Mode Enabled: BME=1)
6:7 CSON 00 Chip Select On Timing
Measured with respect to Address Valid
00 - CS_ valid with address valid
01 - CS_ valid 1 clock after address valid
10 - CS_ valid 2 clocks after address valid
11 - CS_ valid 3 clocks after address valid
8:9 OEON 00 Output Enable On Timing
Measured with respect to CS_ assertion
00 - OE_ valid with chip select valid
01 - OE_ valid 1 clock after chip select valid
10 - OE_ valid 2 clocks after chip select valid
11 - OE_ valid 3 clocks after chip select valid
On writes, controls when write data output driven valid with re-
spect to CS_ assertion.
10:11 WEON 00 Write Enable On Timing
Measured with respect to CS_ assertion
00 - WE_ valid with chip select valid
01 - WE_ valid 1 clock after chip select valid
10 - WE_ valid 2 clocks after chip select valid
11 - WE_ valid 3 clocks after chip select valid