IBM CPC700, Руководство пользователя

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3-6 Processor Interface
Please refer to the processor’s user’s manual for additional information on transfer type encodings.
3.6 Processor to Memory
The processor interface contains a single 32 byte write buffer and a single 8 byte read buffer for processor
accesses to system memory. Once the processor has gained access to memory for a given transfer, the
memory is unavailable for PCI to memory transfers or subsequent processor to memory transfers until the
address tenure of the current access completes.
Reads: Processor to memory read (single beat and burst) data is buffered in the 8 byte read buffer which
captures the data directly from the memory bus and drives the data onto the processor bus in the next
clock cycle. All processor to memory read cycles execute as connected data tenures between the proces-
sor bus and the memory bus.
Writes: All processor write (burst or single beat) cycles are posted. All processor memory read cycles (sin-
gle beat and burst) which hit in the posted write buffer, flush the write buffer contents to memory. All single
beat write cycles flush the posted write buffer (if allocated) before completing. Prior to allowing a PCI
access to system memory, the 32 byte posted write buffer is snooped in addition to the processor’s L1
cache.
Write Buffer: Once data is posted in the processor to memory write buffer it is flushed to memory at the
earliest available opportunity. In general, the posted write buffer has the lowest priority for access to sys-
tem memory; however, the low priority write buffer flush may transition to a high priority write buffer flush
under the following circumstances:
1. Processor to memory read hit in write buffer
2. Any processor to memory write
3. PCI to memory read hit/write hit in write buffer or processor L1
4. Processor read/write to PLB or DCR configuration space
5. If no memory controller requests from the processor and PCI, and memory controller interface is
idle.
6. Snoop push detected.
Note: The processor to memory write buffer is not flushed to system memory until a high priority write
buffer flush request is generated.
1100 TLB invalidate Address only Assert AACK_N, No other response, No PLB
transaction
1101 Read atomic, lwarx SBR or burst Memory read PLB read
1110 External control in,
eciwx SBR Reserved
Assert AACK_N and TA_N. All 1’s returned on
60x Data Bus. MCP_N asserted if MCP_N asser-
tion is enabled.
1111 Read with intent to
modify atomic, stwcx Burst Memory read PLB read
Table 7. Supported Processor Transfer Type Encodings/Response (Continued)
TT[0:3]
Processor
Operation Proc Bus
Transaction CPC700 Response for
Proc to Memory CPC700 Response for
Proc to PLB