Harris DX 25U, Техническое руководство

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J.2.6
Analog Divider (U10)
The Analog Divider IC U10 compensates for variations in the
+230 VDC supply and reduces hum and noise. If the feedback
voltage from the +230 VDC supply increases, the output from
the analog divider will decrease. If the feedback voltage from the
+230 VDC supply decreases, the output from the analog divider
will increase.
The -(Audio + DC) output of U7-7 is fed to U10-6, an Analog
Multiplier IC connected as an analog divider. A sample from the
+230 VDC supply from U12-7 is fed into the input U10-10.
Resistor R17 sets the “scaling factor” so that the output at
U10-8/4 is a signal defined as [(Audio + DC)/power supply
sample voltage x 4.93].
J.2.6.1
Power Supply Sample Circuit
The “power supply sample” voltage at TP5 and U10-10 is deter-
mined by the ”supply sample" voltage divider on Fuse Board A24
and the gain of non-inverting buffer amplifier U12. The high voltage
supply sample from Fuse Board A24 enters the Analog Input Board
at J5-8 through choke L5 and P1. Inductor L5 is a common-mode
choke, which cancels any noise induced in the wiring between Fuse
Board A24 and the Analog Input Board. Some filtering for low
frequency THD optimization is performed by C51 and R52. P1 is
used during factory test.
A voltage from the supply current sample circuits on the LED
Board is brought in through J4-29, CR22 and CR21 and is
applied to U12-5 if there is a current overload fault. This will
cause the output of U12 to increase and reduce output power.
When the high voltage supply is off, the output of U12-7 is zero.
This could also occur if a power supply sample circuit fault
occurs. With no voltage at U10-10, the output U10-8/4 would
increase toward the -15 Volt supply and the transmitter power
output would increase to a high level.
To prevent this, diode CR9 will conduct to maintain the voltage
at U10 pin 10 and TP5 at about +3.9 Volts. When the power
supply sample is normal, CR9 cathode is more positive than the
anode and the diode is cut off.
J.2.7
Digitally Controlled Potentiometer (U8)
Integrated Circuit U8 is a 3-1/2 digit Digitally Controlled Poten-
tiometer (an attenuator). A 12-bit BCD (Binary Coded Decimal)
input from the Controller at U8-4 through U8-15 controls the
output of U8. The digital power control logic inputs will be logic
LOW, near zero Volts, or logic HIGH, near +15 Volts. The output
of U8-1 is buffered by U11. The output of U11-6 at TP-7 will be
from 0.000 to 0.999 times the input U8-17. The DC component
at TP-7 determines the carrier power, and the audio component
modulates the transmitter output.
At 30 kW with 100% modulation, the (Audio + DC) output will
be a 2 Vp-p audio signal with a +1.0 VDC component. At lower
power levels, both the audio and DC components will be less.
The DC voltage at TP-7 will change when the RAISE and
LOWER buttons are depressed, or when the transmitter is
switched between HIGH, MEDIUM and LOW power levels. The
audio signal will also change proportionally with the DC com-
ponent.
J.2.7.1
BCD Logic Input To U8
The BCD power control signal is generated on the Controller and
enters the Analog Input Board at J4. Pull-down resistors, in DIP
resistor arrays R47 and R48, ensure that each line is at ground
unless one of the tri-state logic outputs from the Controller pulls
that line HIGH.
The BCD Power Control data is stored in TTL latches U17 and
U18. Six bits of the 12 bit signal are stored in each latch. The
“RESET” and “CLOCK” inputs of the latches are tied together.
The clock input is the Data Strobe-H (logic HIGH) input from
the Controller through Schmitt Trigger U13. This will delay the
Data Strobe-H signal slightly to ensure that the BCD information
on the inputs of the latches is correct.
Data stored in latches U17 and U18 will change when a transition
from LOW to HIGH logic level occurs at the CLOCK input (pin
11) of each latch. The latch will store the data present at its inputs
at that instant, and that data will then remain in the latch until the
latch is either RESET or another positive-going transition occurs
at the CLOCK input.
If a Data Clear-L (logic LOW) signal from Controller occurs, the
RESET input of each latch will be pulled LOW and the BCD
outputs will go LOW (corresponding to zero power output from
the Power Amplifier stage). The Data Clear-L input is delayed
by two sections of U13 and goes to the “RESET” inputs of U17
and U18.
The BCD output data from U17 and U18 is converted to CMOS
logic levels (+15 VDC for logic HIGH) for U8 by hex level
shifters U14 and U16. Outputs D1 through D4 are the binary bits
for the first (most significant) decimal digit, D5 through D8 are
the bits for the second decimal digit, and D9 through D12 are the
bits for the third (least significant) decimal digit.
If outputs D1 through D12 were “0000/0000/0000” from a BCD
number of 0.000, the digital potentiometer U8 would be at
maximum attenuation and the DC voltage at TP-7 would be 0.0
VDC. This would result in no carrier power.
For a BCD input of 0.999, D1 through D12 would be “1001 1001
1001”, digital potentiometer U8 would be at minimum attenu-
ation and the voltage at TP-7 would be +1.0 VDC. This would
result in a carrier power of 30 kW.
J.2.8
Analog Buffer (U4)
The (Audio + DC) output of U11-6 at TP-7 feeds buffer U4-3 which
is a non-inverting amplifier with a gain of +2. Series resistor R82
and JFET switch Q7 in the PA Turn Off circuit form a voltage divider
to ground at U4-3. When Q7 is turned ON, the (Audio + DC) input
to U4-3 will be pulled to zero, so the Power Amplifier stage output
will be zero (all PA Modules are turned off).
J.2.8.1 PA Turn On/Turn Off Circuit (U13-2, Q1, Q7, U13-4,
Q2, Q8)
The Q2 and Q8 circuitry is identical to that of Q1 and Q7 with
the exception of additional components used to create the “Half
Power Step-Up” during the turn on sequence.
DX-25U
J-2 888-2297-002
WARNING: Disconnect primary power prior to servicing.