Harris DX 25U, Техническое руководство

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lock inputs. If the +30 Vdc supply fails, an Interlock Fault output
is generated which turns the transmitter OFF.
P.7.2
Interlock Status Logic: Outputs
There are three outputs from interlock fault logic on the Con-
troller:
a. Door Interlock Status. To status indicator circuits on the
LED Board. If a Door interlock is active, the DOOR
INTERLOCK LED on the ColorStat™ panel will be
RED.
b. External Interlock Status. To status indicator circuits on
the LED Board. If an External interlock is active, the EXT.
INTERLOCK LED on the ColorStat™ panel will be
RED.
c. Interlock Fault-H. To Type 1 Fault gate U51-8. If either a
Door or an External interlock is active, the Type 1 Fault
gate will generate an OFF command and inhibit PA Power
Supply contactor K2.
P.7.3
Interlock Status Logic: Basic Circuit Description
Both the Door and External interlock circuits are similar and
can be divided into the following stages:
a. Input transistor
b. Delay circuit
c. Pulse stretcher, one-shot
d. “OR” gate
P.7.3.1
Input Transistor: Function
The input transistors convert the signal from the Interlock
String, Door Interlock and External Interlock relays into the
correct logic signal for the interlock circuits on the Controller.
P.7.3.2 Delay Circuit: Function
The DELAY prevents an “OFF” command when AC power fails
and interlock relay K3 de-energizes. A fault-induced “Off”
command would prevent the transmitter from recycling back
ON when AC power returns. The delay is long enough (about
0.15 second) to allow +5 Volt supplies to discharge, disabling
command input circuits. A diode in the delay circuit provides a
“fast” reset (about 10 milliseconds) when the interlock fault
clears.
P.7.3.3
Pulse Stretcher: Function.
The pulse stretcher ensures that any interlock fault generates a
“Fault” output that is long enough to latch the transmitter OFF.
P.7.3.4 “NOR” Gate: Function
The “OR” gate output goes LOW (“Fault output”) either when
the pulse stretcher “Fault” output is present or when an “Inter-
lock Fault” exists or both. The Interlock Fault output will then
be present for as long as an interlock fault is present (but for at
least the pulse stretcher’s 0.5 second output if the interlock fault
is only momentary).
P.7.4
External Interlock: Normal Operation
When the External Interlock is closed (no fault present), the base
of Q8 is grounded (logic LOW) and Q8 is OFF. The collector
goes HIGH and charges C83 to approxi5 Vdc through
R56 and R58. The input to U50-9 is HIGH and U50-8 is LOW.
The pulse stretcher “B” input U61-10 is LOW, and the “Q”
output U61-5 is LOW. Both inputs to U60-2 and U60-3 are
LOW and U60-1 is HIGH.
P.7.5
Door Interlock: Normal Operation
When the Door Interlock is closed (no fault present), Q9-2 is
grounded (logic LOW) and the transistor is OFF. The collector
goes HIGH and charges C81 to approxi5 Vdc through
R47 and R55. The input to U50-5 is HIGH and U50-6 is LOW.
The pulse stretcher “B” input of U61-2 is LOW, and the “Q”
output U61-13 is LOW. Both inputs to U60-5 and U60-6 are
LOW and U60-4 is HIGH.
P.7.5.1 Interlock Gate circuit
Each interlock circuit output from U60-1 or U60-4 is logic
HIGH when there is no interlock fault. Each output goes to the
LED Board status indicator circuits at J7-37 and J7-35, and to
the “Interlock Gate” circuit U51-11 and U60-10/13.
The output of U60-4 is inverted to logic LOW at U60-10 and
U60-1 is inverted to logic LOW at U60-13. These signals are
gated together by U51 and the normal output at U51-11 will be
logic LOW. This logic LOW is fed to U51-10. The other input
to U59-9 is a TYPE 1 Fault input from the LED Board. During
normal operation, U51-8 will be logic LOW.
If a Door or External Interlock occurs, the output of U51-11 will
go HIGH and generate a latched OFF command through Q5-7.
The interlock fault will also turn OFF (Inhibit) K2 through
U52-8.
The output of U51-8 will go HIGH and energize Q5-6 to
generate a latched OFF command. ) output from U60-4 and the
“External Interlock Fault” (Fault LOW) output from U60-1 are
inverted by U60-10 and U60-13 (two-input gates with the inputs
tied together to use as inverters). The inverted, logic HIGH if
fault signals go to OR gate U51-10. A Door Interlock Fault or
an External Interlock Fault (or both) will cause an “Interlock
Fault” logic HIGH output from U51-8.
P.7.6
External Interlock: Fault Condition
An External Interlock fault generates a HIGH input at J5-13 and
turns Q8 ON. The collector goes LOW and discharges C83
through R133 which generates the 0.15 second delay. The
output of U50-8 will go HIGH and trigger pulse stretcher
U61B-5. This pulse ensures that the “Fault-L” output will
remain for at least 0.5 second. The pulse width is determined by
the RC network at the one-shot’s “CR” terminal. The HIGH
input to U60-2 and U60-3 will bring U60-1 LOW. The LOW
input will force U60-13 HIGH.
P.7.7
Door Interlock: Fault Condition
A Door Interlock fault generates a HIGH input at J5-15 and
turns Q9 ON. Q9-1 goes LOW and discharges C81 through R47
which generates the 0.15 second delay. The output of U50-6 will
go HIGH and trigger pulse stretcher U61A-13. This pulse
ensures that the “Fault-L” output will remain for at least 0.5
second. The pulse width is determined by the RC network at the
one-shot’s “CR” terminal. The HIGH input to U60-6 and U60-5
DX-25U
P-16 888-2297-002 Rev. S: 05-02-97
WARNING: Disconnect primary power prior to servicing.