Harris DX 25U, Техническое руководство

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L.3.1.2
Modulated B- Supply
The Modulated B- Supply is brought into the board at J19-1 and
is applied to the outputs of the driver IC’s through pull-down
resistors. RF amplifier turn-on/turn-off times depend on the load
on the modules, that is, on the total number of modules turned
ON at any moment. To compensate for changes in turn-on/turn-
off times, the timing of the control circuits is varied with modu-
lation. This “active bias” voltage is provided by the Modulated
B- supply from the DC Regulator. Refer to SECTION M, DC
Regulator, for a description of the B+ Supply and Modulated B-
Supply.
L.3.1.3 +22 VDC supply
Unreg22 VDC is brought into the board at J19-9 for the
Blown Fuse and Cable Interlock circuits. This supply is present
on the Modulation Encoders whenever the Low Voltage is ON.
L.3.2
Digital Audio Data Circuits
The 12-bit digital word from the Analog to Digital Converter
enters at J17-2 through J17-24 (odd numbered pins are ground).
Resistive dividers R10 and R11 provide “pull-up” and “pull-
down” functions and are only installed on Modulation Encoder
A37. When a LOW-to-HIGH transition appears at the “Clock”
input of data latches U49 and U50, the digital data on the inputs
will be latched through to the outputs. The DATA STROBE-L
(LOW) signal at J17-26 from the Analog to Digital Converter is
inverted by U57. The latch outputs will then remain in that logic
state until the next DATA STROBE-L signal latches the next
digital audio word or a PA TURN OFF-L (LOW) signal appears
at the latch “Clear” inputs. When the “Clear” input is LOW, all
latch outputs go to a logic LOW which turns all PA Modules OFF.
L.3.2.1 “Binary Step” Digital Audio Circuits
Six bits (B7 through B12) are inputs to data latch U51. The
outputs of U51 go through U60 and U61 and then to a jumper
configuration comprised of P8-A,B,C, and D. The A37 Modula-
tion Encoder uses position P8-D, which connects B7 through
B12 to the Inverter/Driver inputs U1, U2, and U40.
L.3.2.2
“Big Step” Digital Audio Circuits
Eight bits (B1 through B8) address U41 through U48. Each ROM
encodes the 8 bits by outputting the digital pattern stored in the
addressed location to latches U31 through U38. The outputs of
U32 through U38 go to Inverter/Drivers U3 through U30, which
provide turn-on/turn-off signals for “Big Step” RF amplifiers on
the Modulation Encoder. On Modulation Encoder A37, U31 only
connects to Inverter/Drivers U39A and U40A to drive two “Big
Step” RF amplifiers.
L.3.3
Inverter/Driver Circuits
The Inverter/Driver Circuits convert a TTL signal to proper
voltages for RF amplifier ON/OFF control. Dual MOS clock
drivers are used to provide turn-on/turn-off inputs to the RF
amplifiers.
L.3.3.1
Simplified Diagram
Refer to the Simplified Inverter/Driver Output circuit diagram
(Figure L-1). The output circuit of the DS0026 driver is taken
from two internal transistors. The collector of the “pull-up”
(current source) transistor is connected to the B+ supply (+5.75
VDC) and the emitter of the “pull-down” (current sink) transistor
is connected to the V- terminal (Gnd). Only one transistor is
turned on at a time, so that the output is pulled to B+ or Gnd. The
driver output feeds a voltage divider, made up of a “pull-up”
resistor in series with the output and a second “pull-down”
resistor connected to the Modulated B- Supply. The resistor
junction is the input to the PA Module turn-on/turn-off control
circuit.
A logic HIGH signal to the input of the Inverter/Driver will cause
the “pull-down” transistor to conduct. The PA Module control
voltage is pulled down to the modulated B- supply, and the RF
amplifier turns ON.
A logic LOW signal to the input of the Inverter/Driver will cause
the “pull-up” transistor to conduct. The PA Module control
voltage is pulled up the +5 VDC B+ supply, and the RF amplifier
turns OFF.
L.3.3.2 Circuit Description
The Inverter/Driver circuit for each RF amplifier is identical.
Therefore, only the circuit for RF33 will be described.
The output at U32-2 provides the turn-on/turn-off signal for “Big
Step” amplifier RF33, through P1-1 (1,2). When the signal is
logic HIGH at this point, RF33 will be turned ON. The latch
output goes to Inverter/Driver U3-2 through isolating resistor
R117 (1,2). Capacitor C117 bypasses high-frequency compo-
nents around R117 to improve pulse rise and fall times at the
input of U3. Pull-down resistor R132 (1,2) will hold U3-2 LOW
if the jumper at P1-1 (1,2) is removed.
L.3.4
Cable Interlock Circuit
The cable interlock circuit will apply a “PAOFF-L” signal to
clear the data latch outputs, illuminate a red “CABLE INTER-
LOCK” LED on the ColorStat™ panel, and illuminate the inter-
lock LED on the Modulation Encoder when:
a. Any of the interconnecting cables between the Modulation
Encoders and the Combiner/Motherboards are discon-
nected.
b. Any PA Modules are not installed.
c. Any Driver Modules are not installed.
d. The power cable from the DC Regulator to either Modu-
lation Encoder is disconnected.
A Cable Interlock Fault will cause the Controller to turn the
transmitter OFF and will not allow the transmitter to be turned
ON until the fault is corrected.
L.3.4.1
Circuit Description
Refer to Mod Encoder Interconnect Diagram, Figure L-2, and
Cable Interlock Circuit Diagram. Figure L-4, and the Mod En-
coder schematic for the following text:
The Modulation Encoder has eight identical interlock circuits
and each circuit monitors eight PA Modules. Each interlock
circuit output is monitored by 10-segment LED display DS1 and
fed to U67. The Driver Modules are interlocked by a circuit on
the Driver Encoder/Temp Sense Board and fed to J18-8 on
Modulation Encoder A37. The fault summary output from Mod
Encoder A37 is fed to the LED Board at J18-10. If any circuit
DX-25U
L-2 888-2297-002 Rev. T2: 06-27-97
WARNING: Disconnect primary power prior to servicing.