Harris DX 25U, Техническое руководство

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ceived from the Power Control logic, but U56A is inhibited at
pin 1 by the “K2 IS CLOSED-H” signal. There are no other
signal changes in the turn-on/turn-off control logic and no
contactors operate.
P.4.2.2
Clock Circuit
Switch Debounce IC U45 generates a 200 Hz clock signal which
is applied to divide-by-eight frequency divider U38 and U24.
The 25 Hz signal is then delayed by U50 and fed to the inputs
of the counter gates. The clock is inhibited by U1-6 until
contactor K2 is energized.
When a RAISE/LOWER command enables the BCD counters,
the clock signal is present on the UP or DWN input to change
the BCD number, and is fed to the Data Strobe Gate through
U1-3/8/11.
P.4.2.3 Data Strobe Circuit
Inputs to Data Strobe gate U13-8 are from the clock signal, the
power level change pulse and the K1 start pulse. The output of
U13-8 is delayed 100 microseconds by the C119 delay circuit,
then strobes the digital power data latches on the Analog Input
Board when:
a. The transmitter is turned ON. The inverted K1 Start Pulse
generates the Data Strobe signal.
b. A Power Level Change occurs. The Power Level Change
pulse from U57-6 generates the Data Strobe signal.
c. The RAISE/LOWER command is active. The clock signal
for the up/down counter generates the Data Strobe signal.
P.4.2.4 Interlock Fault Circuit
The Interlock Fault Circuit gates the interlock inputs and gen-
erates an “INTLK FAULT-H” output which is gated with the
TYPE 1 FAULT input to generate a Fault Induced OFF com-
mand. The TYPE 1 FAULT output also is applied to U52-11 to
inhibit contactor K2. Inputs to the Interlock Fault Circuit are:
a. Door Interlock. Generates an OFF command if any inter-
locked door on the transmitter is open.
b. External Interlock. Generates an OFF command if any
external interlocked component is not in a safe condition.
c. Interlock String. Generates an OFF command if there is
loss of supply voltage to the external and door interlock
circuits.
P.4.2.5
Supply Fault Circuit
The Supply Fault Circuit monitors the low voltage regulators on
the Controller. If any regulator fails, the circuit will generate a
“SUPPLY FAULT-L” signal which:
a. Inhibits the command signal decode IC U42. This pre-
vents any command input from being recognized.
b. Inhibits the Power Level Change gate U57-6. This pre-
vents any command input from being clocked into Power
Level Latch U40.
c. Clears the Power Latch circuits on the Analog Input
Board. This brings the power control data lines to zero.
d. Clears the turn-on one-shot IC U56A-13. This prevents
generation of a K1 turn-on pulse.
e. Inhibits K2. This will de-energize the K2 contactor if the
transmitter is ON.
P.5
Turn-on/Turn-off Control Logic: Cir-
cuit Descriptions
The following paragraphs describe operation of one-shot, input,
and delay timer circuits in the Turn-On/Turn-Off Control Logic.
Refer to the Controller Schematic, 843-5400-091, in the Draw-
ing Package.
P.5.1
“K1 Turn-on One-Shot” (Monostable U56A-
13)
U56A is one-half of a 74HC123 dual monostable multivibrator,
or “one-shot.” In the “normal” state, U56-13 “Q” output is
LOW and U56-4 “Q-not” output is HIGH. When the one-shot
is triggered, a 1.6 second logic HIGH pulse is generated at
U56-13 and a 1.6 second logic LOW pulse is generated at pin
4. The pulse width is determined by an R-C network at pin 15,
the “RC” input.
When the one-shot is INHIBITED, it cannot be triggered, but if
an INHIBIT input occurs during a one-shot pulse, the 1.6 second
pulse will be completed. When the one-shot is CLEARED, the
output pulse is stopped immediately; the “Q” output goes LOW
and the “Q-not” output goes HIGH.
P.5.1.1 TRIGGER:
If no fault or inhibit signals are present, the one-shot is TRIG-
GERED by one of two methods:
a. A low to high transition at U56-2 “B” input. This Trigger
transition is the rising edge of the “TURN-ON RE-
QUEST-H” logic signal from the power control section.
b. A low to high transition at the “clear” input, assuming “A”
input is low and “B” input is high. This trigger transition
is the rising edge of the delayed supply fault from the local
regulators.
P.5.1.2
CLEAR:
A FAULT or an “OFF” command will CLEAR the one-shot
during the step-start cycle, and will prevent it from triggering
again. When U56-3 “CLR” input goes LOW, the “Q” output
goes LOW and the “Q-not” output goes HIGH. The 1.6-second
“Turn-on” pulse is stopped immediately, aborting the turn-on
sequence, and K1 de-energizes. If a fault or “Off” command
holds the CLEAR input LOW, the one-shot cannot trigger again.
(A fault or “Off” command also de-energizes K2). The follow-
ing conditions cause a CLEAR-L input and clear U56A:
a. SUPPLY FAULT-L, to U53-12
b. INHIBIT K2-L, to U53-13
The “INHIBIT K2-L” at U52-8 is generated by any of three
conditions:
1. TYPE 1 FAULT-H, at U52-10
2. TYPE 2 FAULT-H, at U52-9
3. OFF-H at U52-11
Section P - Controller (A38)
Rev. S: 05-02-97 888-2297-002 P-5
WARNING: Disconnect primary power prior to servicing.