Harris DX 25U, Техническое руководство

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b. RF DRIVE SWITCH-OVER: NOR gate U3-10 is also a
VSWR Fault - L signal to one-shot U28A which generates
a “RF Drive Switch-Over” pulse to the Oscillator.
c.
VSWR SELF-TEST CIRCUIT INPUT: NOR
gate U3C output
also provides a “VSWR Fault-L” signal to the VSWR
Self-Test Circuit.
BANDPASS FILTER VSWR:
a. 0.5 Second RED “Bandpass Filter VSWR” status indica-
tion on the ColorStat™ panel.
b. 0.5 Second External “Bandpass Filter VSWR” status in-
dication (at TB1-8).
ANTENNA VSWR:
a. 0.5 Second RED “Antenna VSWR” status indication on
the ColorStat™ panel.
b. 0.5 Second External “Antenna VSWR” indication (at
TB1-9).
Q.5.4.1.2
Multiple VSWR Fault Action
If enough repeated VSWR “trips” occur, the LED Board VSWR
logic will take further action, as follows:
a. A Status Indicator latch will provide a latched VSWR
indication on the ColorStat™ panel until the status indi-
cator circuits are RESET.
b. A VSWR-Induced LOWER command will be generated.
The VSWR-Induced Lower command goes to the Power
Control logic on the Controller. Power will be lowered
until the reflected power is below the 1500 Watt peak
envelope power VSWR detection threshold.
Q.5.4.2
VSWR Logic: Circuit Descriptions
The following description refers to Figure Q-5, VSWR Logic
Simplified Diagram. VSWR logic is shown on Sheet 2 of the
LED Board schematic diagram.
The “Bandpass Filter” VSWR signal input goes through gates
U3-1 and U3-4, and “Delay” U19-11. If both “Bandpass Filter”
and “Antenna” VSWR problems are detected at the same time,
the two logic LOW inputs to gate U3-1 cause its output to go
HIGH. The logic HIGH input to “Inhibit” gate U3-4 holds its
output LOW so that only the “Antenna” VSWR fault will be
detected. The gate propagation time of gate U19-11 provides a
slight delay to match the delay through U3-1.
The “Antenna” VSWR signal is inverted by U3-13. The invertor
output is a logic HIGH pulse when a VSWR fault is detected, and
goes to VSWR NOR gate U3-10 and Antenna VSWR one-shot
U12A.
Q.5.4.2.1
“NOR” Gate: U3-10
When either a Bandpass Filter VSWR fault or an Antenna
VSWR fault is detected, U3-10 goes LOW and drives PA Off
gate U40, VSWR self-test latch U42A, and “RF Drive Switch-
over” one-shot U28A.
Q.5.4.2.2
“Pulse Stretch”: U12A and U12B
Both U12B and U12A operate in the same way; when a VSWR
fault is detected, the logic LOW to HIGH transition at the “B”
input triggers the one-shot which generates a 0.5 second logic
HIGH pulse at the Q output and a 0.5 second logic LOW pulse
at the NOT-Q output. The one-shots are retriggerable, so that if
another VSWR fault is detected during the 0.5 second pulse
output the output pulse will be “extended” another 0.5 second.
The one-shots are inhibited by the “Supply Fault-L” signal from
the Controller during turn-on, when changing voltages could
cause false “VSWR” logic signals.
Q.5.4.3 Generating Type 3 Faults (VSWR Logic Circuit De-
scription)
Refer to Figure Q-5, VSWR Logic Simplified Diagram, and to
the VSWR Logic circuits on Sheet 2 of the LED Board sche-
matic, 839-7855-184.
Q.5.4.3.1
Detecting Multiple VSWR “Hits”:
When an impedance mismatch causes a number of VSWR “hits”
to occur in rapid succession, the time between detected VSWR
“hits” is less than the length of the logic HIGH pulse at the R-C
network to Schmitt Trigger inputs U4-1 and U4-5. (Each time the
transmitter PA comes back ON, another VSWR fault will be
detected). During the 14 (or 19) millisecond pulse, the capacitor
charges, and between pulses it discharges back into the current sink
provided by the logic LOW output of U3-4 or U3-8. A series of 20
to 30 “hits” will charge the capacitor above the threshold voltage
of the inverting Schmitt Trigger. The inverting Schmitt trigger
output goes low and is inverted again to generate a logic HIGH
input to the “Status Indicate Latch” circuit.
Q.5.4.3.2
“Status Indicate Latch” Circuits: U23-6/U24A and U23-
3/U24B
A LOW-to-HIGH transition from the “multiple VSWR” circuit,
U4-4 or U4-8, triggers the latch through U23-3 or U23-6, the Q
output goes HIGH and the NOT-Q output goes LOW. Refer to
the description of “Reset A and Reset B Operation” earlier in
this section for a further description of these Latch circuits.
Q.5.4.3.3
“VSWR Induced Lower” Circuits: U22-3/6, U37-6,
U28B
The following description refers to the Bandpass Filter VSWR
circuit (U4-6/8 and U22-6), but operation of the Antenna VSWR
circuit is identical (U4-2/4 and U22-3). When multiple (re-
peated) VSWR “hits” cause the output of U4D to go HIGH, one
input to AND gate U22 will go HIGH and additional repeated
logic HIGH VSWR pulses will appear at the output of U22-6.
The ANTENNA and BPF VSWR pulses are applied to OR gate
U37-6. The pulses appear at U37-6 and at the “B” input of
one-shot U28B.
When “VSWR-induced lower” one-shot U28 is triggered (via pin
10), it generates a 47 millisecond logic HIGH pulse. Each addi-
tional VSWR “hit” will extend the pulse by an additional 47
milliseconds.
The logic HIGH output at pin 5 of U28 is the “VSWR Induced
Lower” command to the Power Control Logic on the Controller.
This signal will lower transmitter output power until the peak
reflected power is below the VSWR detection threshold set on
the Output Monitor.
Section Q - LED Board (A32)
Rev. R: 11-11-96 888-2297-002 Q-13
WARNING: Disconnect primary power prior to servicing.