361
CHAPTER 17 FLASH MEMORY
17.3
Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, and Chip Erase.
■
Command Sequence Table
Table 17.3-1 lists the commands used for flash memory write/erase.
Table 17.3-1 Command Sequence Table
Command
sequence
Bus
write
access
1st bus write
cycle
2nd bus write
cycle
3rd bus write
cycle
4th bus read/
write cycle
5th bus write
cycle
6th bus write
cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Read/Reset
(*)
1
XXXX
F0
-
-
-
-
-
-
-
-
-
-
4
FAAA
AA
F554
55
FAAA
F0
RA
RD
-
-
-
-
Write
program
4
FAAA
AA
F554
55
FAAA
A0
PA
PD
-
-
-
-
Chip Erase
6
FAAA
AA
F554
55
FAAA
80
FAAA
AA
F554
55
FAAA
10
*: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
Notes:
•
The addresses shown in the table are those on the CPU memory map. All addresses and data are represented in
hexadecimal notation. The letter X indicates an appropriate value.
RA: Read address
PA: Write address.
RD: Read data
PD: Write data.
•
The flash memory can only accept the command sequences mentioned on the above table (Read/Reset, Write
program, Chip Erase), other command sequences are strictly prohibited to be sent to the flash memory or else the
flash memory may become malfunction.
Содержание F2MC-8L F202RA
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Страница 90: ...74 CHAPTER 3 CPU ...
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Страница 150: ...134 CHAPTER 6 WATCHDOG TIMER ...
Страница 174: ...158 CHAPTER 7 8 BIT PWM TIMER User processing POPW A XCHW A T Restoring A and T POPW A RETI ENDS ...
Страница 176: ...160 CHAPTER 7 8 BIT PWM TIMER ...
Страница 220: ...204 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER ...
Страница 240: ...224 CHAPTER 9 12 BIT PPG TIMER ...
Страница 258: ...242 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END ...
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Страница 371: ...355 CHAPTER 16 WILD REGISTER FUNCTION 16 3 5 Data Test Set Register WROR A test register Do not access this register ...
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