114
CHAPTER 4 I/O PORTS
●
Coding example
PDR0 EQU
0000H
; Address of port 0 data register
DDR0 EQU
0001H
; Address of port 0 data direction register
PDR3 EQU
000CH
; Address of port 3 data register
DDR3 EQU
000DH
; Address of port 3 data direction register
;------------------------------Main program-----------------------------------------------------------------------
CSEG
; [CODE SEGMENT]
:
CLRB PDR0:0
; Set P00 at "L" level.
MOV PDR3,#11111111B
; Set all pins of port 3 at "H" level.
MOV DDR0,#11111111B
; Set P00 to function as an output port by coding
#XXXXXXX1B.
MOV DDR3,#11111111B
; Set all bits of DDR3 such that all pins of port 3 function
as an output port.
:
ENDS
;---------------------------------------------------------------------------------------------------------------------
END
Содержание F2MC-8L F202RA
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Страница 32: ...16 CHAPTER 1 OVERVIEW ...
Страница 90: ...74 CHAPTER 3 CPU ...
Страница 142: ...126 CHAPTER 5 TIME BASE TIMER POPW A RETI ENDS END ...
Страница 150: ...134 CHAPTER 6 WATCHDOG TIMER ...
Страница 174: ...158 CHAPTER 7 8 BIT PWM TIMER User processing POPW A XCHW A T Restoring A and T POPW A RETI ENDS ...
Страница 176: ...160 CHAPTER 7 8 BIT PWM TIMER ...
Страница 220: ...204 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER ...
Страница 240: ...224 CHAPTER 9 12 BIT PPG TIMER ...
Страница 258: ...242 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END ...
Страница 274: ...258 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL ...
Страница 362: ...346 CHAPTER 15 BUZZER OUTPUT ...
Страница 371: ...355 CHAPTER 16 WILD REGISTER FUNCTION 16 3 5 Data Test Set Register WROR A test register Do not access this register ...
Страница 390: ...374 CHAPTER 17 FLASH MEMORY ...
Страница 419: ...403 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Страница 434: ...418 INDEX ...
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