Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XE-Family Reference Manual , Rev. 1.19
700
Freescale Semiconductor
19.3.2.4
PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Read: Anytime
Write: Anytime
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
s
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
0
PCKB2
PCKB1
PCKB0
0
PCKA2
PCKA1
PCKA0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-6. PWM Prescale Clock Select Register (PWMPRCLK)
Field
Description
6–4
PCKB[2:0]
Prescaler Select for Clock B
— Clock B is one of two clock sources which can be used for channels 2, 3, 6, or
7. These three bits determine the rate of clock B, as shown in
2–0
PCKA[2:0]
Prescaler Select for Clock A
— Clock A is one of two clock sources which can be used for channels 0, 1, 4 or
5. These three bits determine the rate of clock A, as shown in
Table 19-2. Clock B Prescaler Selects
PCKB2
PCKB1
PCKB0
Value of Clock B
0
0
0
Bus clock
0
0
1
Bus clock / 2
0
1
0
Bus clock / 4
0
1
1
Bus clock / 8
1
0
0
Bus clock / 16
1
0
1
Bus clock / 32
1
1
0
Bus clock / 64
1
1
1
Bus clock / 128
Table 19-3. Clock A Prescaler Selects
PCKA2
PCKA1
PCKA0
Value of Clock A
0
0
0
Bus clock
0
0
1
Bus clock / 2
0
1
0
Bus clock / 4
0
1
1
Bus clock / 8
1
0
0
Bus clock / 16
1
0
1
Bus clock / 32
1
1
0
Bus clock / 64
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
S12XE
products
in
208
MAPBGA
packages