Fluke 5790A, Руководство оператора

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Remote Operation
Checking 5790A Status
5
5-19
5-34. Instrument Status Register (ISR)
The Instrument Status Register (ISR) gives the controller access to the state of the
5790A, including some of the information presented to the operator on the Control
Display and the display annunciators during local operation.
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
PON 0 CME EXE DDE QYE 0 OPC
PON Power on. This bit is set to 1 if line power has been turned off and on since the last time the ESR
was read.
CME Command error. The 5790A's IEEE-488 interface encountered an incorrectly formed command.
(The command ERR? fetches the earliest error code in the error queue, which contains error
codes for the first 15 errors that have occurred.)
EXE xecution error. An error occurred while the 5790A tried to execute the last command. This could
be caused, for example, by a parameter bein g out of range. (The command ERR? fetches the
earliest error in the error queue, which contains error codes for the first 15 errors that have
occurred.)
DDE Device-dependent error. An error related to a device-dependent command has occurred.
QYE Query error. The 5790A was addressed to talk when no response data was available or
appropriate, or when the controller failed to retrieve data on the output queue.
OPC Operation complete. All commands previous to reception of a *OPC c ommand have been executed,
and the interface is ready to accept another message.
add49f.eps
Figure 5-3. Bit Assignments for ESE and ESE
5-35. Instrument Status Change Registers
There are two registers dedicated to monitoring changes in the ISR. These are the ISCR0
(Instrument Status 1-0 Change Register) and the ISCR1 (Instrument Status 0-1 Change
Register). Each status change register has an associated mask register. Each ISCR is
cleared (set to 0) when the 5790A is turned on, every time it is read, and at each *CLS
(Clear Status) command.
5-36. Instrument Status Change Enable Registers
The Instrument Status Change Enable registers (ISCE0 and ISCE1) are mask registers for
the ISCR0 and ISCR1 registers. If a bit in the ISCE is enabled (set to 1) and the
corresponding bit in the ISCR makes the appropriate transition, the ISCB bit in the Status
Byte is set to 1. If all bits in the ISCE are disabled (set to 0), the ISCB bit in the Status
Byte never goes to 1. The contents of the ISCE registers are set to 0 at power-up.
5-37. Bit Assignments for the ISR, ISCR, and ISCE
The bits in the Instrument Status, Instrument Status Change, and Instrument Status
Change Enable registers