3.2
Powerup and powerdown sequences
The ON/OFF/Soft Reset, PBON, the Hardware Reset button, PBRESET, and powerdown requests from
the operating system initiate the powerup and powerdown sequences.
Powerup sequence from powered down state
The powerup sequence of the N1 board is as follows:
1. The PC tower is switched on using the power switch.
2. The
Motherboard Configuration Controller
(MCC) and the
Platform Controller Chip
(PCC) are
powered from SB_3V3. All other supplies are powered off.
3. The MCC powers the EEPROM on the board and reads it to determine the HBI code for the board.
4. The system enables the MCC command-line interface on UART0.
5. The system enables the configuration microSD card. You can connect a workstation to the DBG USB
port to edit existing configuration files or Drag-and-Drop new configuration files.
6. The system waits in standby state.
7. The PBON button is pressed briefly.
8. The system loads the board configuration file:
• The MCC reads the generic
config.txt
file.
• The MCC searches the configuration microSD card MB directory for a directory name that
matches the board HBI number.
9. If the MCC finds configuration subdirectories that match the HBI code of the board, configuration
continues and the MCC reads the
board.txt
file.
10. If the MCC does not find the correct configuration subdirectories or files, it records the failure to a
log file on configuration microSD card. Configuration stops and the system reenters the standby state.
11. The MCC enables the ATXPSU (ATXON).
12. The MCC takes the PCC out of reset in the Enterprise user case.
13. The MCC enables all the supplies, including the board VIO, and the N1 SoC and IOFPGA supplies.
14. The MCC enables the
System Control Processor
(SCP) 32kHZ clock,
REFCLK
, and the board
clocks.
15. The MCC reads the FPGA image from the configuration microSD card and loads it into the IOFPGA.
16. The MCC sets the board oscillator frequencies using values from the
board.txt
file.
17. The MCC releases the
Serial Configuration Controller
(SCC) reset,
nCFG_RESET
.
18. If necessary, the MCC programs the IOFPGA and N1 SoC SCC registers as a backup procedure.
19. The MCC programs the SCP and MCP QSPI images from the
images.txt
file.
20. The MCC notifies the PCC that the N1 SoC is coming out of reset and then releases
nSRST
.
21. The MCC releases
nPOR
to the N1 SoC.
22. The MCC enters run state enabling the USBMSD and monitors the MCC UART interface for user
commands. It also communicates with the PCC.
23. The SCP and
Manageability Control Processor
(MCP) boot from internal ROM.
24. The SCP and MCP run code from their QSPI flash.
25. The SCP performs the basic N1 SoC setup, PLLs, internal clocks.
26. The SCP releases the
Power Policy Units
(PPUs) to begin the application boot sequence.
27. Application code runs on the N1 SoC. The system is in the operating state.
Powerdown sequence
A long press, greater than two seconds, of the PBON button, initiates the powerdown sequence. The
powerdown sequence is as follows:
1. Press the PBON button for longer than two seconds.
2. The PCC detects the power request and sequences the power down with the SCP.
3. The SCP signals the powerdown request to the application processor, that is, one of the N1 clusters.
4. The application cluster goes through its cleanup and shutdown sequence.
5. The application cluster goes to the
Wait for Interrupt
(WFI) state.
6. The PPU sees the WFI state and powers down. The SCP waits for this sequence to complete.
7. The SCP powers down all supplies.
8. The SCP signals the PCC that it is ready for shutdown using the I
2
C bus.
3 Configuration
3.2 Powerup and powerdown sequences
101489_0000_02_en
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