Table 4-13 SCC registers summary (continued)
Offset
Name
Type Reset
Width Description
0x0FF8
COMPID2
RO
0x0000_0005
32
Component ID2 register
See
0x0FFC
COMPID3
RO
0x0000_00B1
32
Component ID3 register
See
4.4.2
SSC_DBGCFG_STAT Register
The SSC_DBGCFG_STAT Register characteristics are:
Purpose
Controls how the Debug Authentication signals are to be driven, either from an external source,
or internally using build-in register bits, also implemented using this register.
Defines the values of the Debug Authentication signals when they are configured to be
internally driven.
Usage constraints
This register is read-only.
Configurations
Available in all N1 board configurations.
Memory offset and full register reset value
See
4.4.1 System Security Control registers summary
The following table shows the SSC_DBGCFG_STAT Register bit assignments.
Table 4-14 SSC_DBGCFG_STAT Register bit assignments
Bits
Name
Type
Function
[31:8]
-
-
Reserved.
[7]
SPIDEN_SEL_STAT
RO
Selects between SPIDEN external or internal
drive:
0b0
: External.
0b1
: Internal.
If external mode is selected SPIDEN is driven
by top-level configuration input
SPIDEN_CFG.
Reset value
0b0
.
[6]
SPIDEN_INT_STAT
RO
SPIDEN internal drive value
Reset value
0b0
.
4 Programmers model
4.4 System Security Control registers
101489_0000_02_en
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