HARDWARE
CPCI-810 User’s Manual
3-7
Revision 1.1, June 2001
The Intelligent Input Output (I
2
O) specification allows architecture-independent I/O subsystems to
communicate with an OS through an abstraction layer. The specification is centered around a message-
passing scheme. An I
2
O-compliant peripheral (IOP) is comprised of memory, processor, and input/
output devices. The IOP dedicates a certain space in its local memory to hold inbound (from the remote
processor) and outbound (to the remote processor) messages. The space is managed as memory-
mapped FIFOs with pointers to this memory maintained through the MPC8240 I
2
O registers. Please
refer to the MPC8240 User’s Manual for I
2
O register descriptions, FIFO descriptions and an I
2
O
message queue example.
3.8.5
JTAG/COP Support
The MPC8240 provides a joint test action group (JTAG) interface. Additionally, the JTAG interface is
also used for accessing the common on-chip processor (COP) function of PowerPC processors. The
COP function of PowerPC processors allows a remote computer system (typically a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The
COP interface connects primarily through the JTAG port of the processor. The 16 pin COP header
(sample part is Samtec # HTSW-108-07-S-S) is located at J23. The COP header adds many benefits
including breakpoints, watchpoints, register and memory examination/modification and other standard
debugger features are possible. The COP header definition is shown if Figure 3-6.
Figure 3-6. COP Header
3.9
GEOGRAPHIC ADDRESSING
CompactPCI backplanes that support 64-bit connector pin assignments are required to provide a unique
differentiation based upon which physical slot the board has been inserted. The CPCI-810 makes this
definition available to the software. The definition for GA[4:0] is shown in Figure 3-7.
TDO 1
TDI 3
VDD 5
TCK7
TMS 9
SRESET# 11
COP_RESET# 13
VDD 15
2 QACK #
4 TRST#
6 VDD
8 CHKSIN#
10 N/C
12 GND
14 N/C
16 GND
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