CyClone COMPACTPCI-810, Руководство пользователя

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CPCI-810 User’s Manual
A-1
Revision 1.1, June 2001
APPENDIX A
PMC MODULE INTERFACE
A.1 INTRODUCTION
The PMC Module Interface allows PCI devices to be connected to the secondary PCI interface of the
CPCI-810 Adapter. The IEEE STD P1386.1, PCI Mezzanine Card (PMC), provides for one set of
clocking and arbitration signals per PMC Module. Cyclone Microsystems has expanded this to two sets
for the PMC Module on the CPCI-810. Otherwise, with a few exceptions, the standard signals defined
for 32-bit CPCI connectors are used for the PMC Modules. The exceptions are noted in section A.3.
The timing for devices on PMC Modules is the same as the timing for any other PCI device; see the
PCI
Local Bus Specification revision 2.1 for details.
A number of PMC Modules are available from Cyclone Microsystems. This section is intended for
users interested in developing their own modules.
A.2 PHYSICAL ATTRIBUTES
Please refer to IEEE P1386/Draft 2.0 for the physical dimensions of PMC modules.
A.3 PMC MODULE SIGNAL DEFINITIONS
PMC Modules use the signals defined in the IEEE STD P1386.1. The following four signals are added
to this definition to handle the expansion from one to three devices per PMC module:
• GNT1#
• REQ1#
• CLK1
• IDSEL1
Please note that the added signals used the PMC-RSVD signals as defined in IEEE STD P1386.1. The
PCI-RSVD remain untouched.
Also, note that GNT1# follow the description for GNT#, REQ1# follow the description for REQ#,
CLK1 follow the description for CLK, and IDSEL1 follow the description for IDSEL. When the
appropriate signals are connected to PCI devices on a PMC Module, each device has the full
complement of PCI signals defined in the specification.
Table A-1 shows the IDSELx# routing and table A-2 shows the interrupt routing on the CPCI-810.
Table A-1. PMC Clock & Arbitration Assignment
IDSEL ADDR IDSEL# CLOCK ARBITRATION
IDSEL# AD16 J12.25 CLKA REQ0#,GNT0#
IDSEL1# AD17 J12.34 CLKB REQ1#,GNT1#
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