MPC8240 PROCESSOR
CPCI-810 User’s Manual
2-3
Revision 1.1, June 2001
2.6
INTERRUPTS
The CPCI-810 interrupt scheme is based upon the MPC8240 processor’s embedded programmable
interrupt controller (EPIC). The EPIC unit is set in the serial interrupt mode. The serial interrupt mode
allows for a maximum of 16 external interrupts. Table 2-1 shows the assignment for the serial
interrupts.
The EPIC interface also contains several internal interrupt sources. These include the four global
timers, the two DMA channels, the I
2
C bus, and from the Message Unit.
In addition to the EPIC interface, errors detected by the MPC8240 are reported to the processor core by
asserting an internal machine check signal Many of the errors detected in the MPC8240 cause
exceptions to be taken by the processor core. The error reporting is provided for three of the primary
interfaces, processor core interface, memory interface, and the PCI interface.
Table 2-1. Serial Interrupt Assignment
2.6.1
Shared PMC Interrupts
The PMC interrupts, INTA, INTB, INTC, and INTD, are received on serial interrupts 4 through 7. To
remain in compliance with the PCI-to-PCI Bridge Specification, Cyclone has implemented the
following SPCI interrupt mapping scheme.
EPIC Serial Interrupt
Interrupt Source
Vector Number
Polarity
0
Primary PCI INTA
0x10
0
1
Primary PCI INTB
0x11
0
2
Primary PCI INTC
0x12
0
3
Primary PCI INTD
0x13
0
4
PMC INTA
0x14
0
5
PMC INTB
0x15
0
6
PMC INTC
0x16
0
7
PMC INTD
0x17
0
8
Ethernet 0 INT
0x18
0
9
Ethernet 1 INT
0x19
0
10
Temperature INT
0x1A
0
11
ENUM
0x1B
0
12
UART INT
0x1C
1
13
Fan INT
0x1D
0
14
Power Supply INT
0x1E
0
15
Not Used
0x1F
x
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