CPCI-810 User’s Manual
2-1
Revision 1.1, June 2001
CHAPTER 2
MPC8240 PROCESSOR
2.1
MPC8240 PROCESSOR
The MPC8240 contains a PowerPC 603e core processor. The core is configured to run at 250 MHz.
This RISC processor utilizes a superscalar architecture that can issue and retire as many as three instruc-
tions per clock. The core features independent 16 Kbyte, four-way set-associative, physically addressed
caches for instructions and data and on-chip instruction and data memory management units (MMUs).
2.2
BYTE ORDERING
The CPCI-810 is designed to run in big endian mode. The byte ordering determines how the core
accessses local memory and the PCI bus. Big endian stores the most significant byte in the lowest
address.
2.3
RESET VECTOR
The 8-bit wide Flash ROM is located in the address range FFE0 0000h through FFFF FFFFh. See
Figure 2.1, the CPCI-810 memory map. The MPC8240 reset vector is located at address FFF0 0100h.
This reset vector location, which contains a branch to the rest of the boot code, is essentially in the
middle of the ROM device. This positioning results in a break up of continuous memory space and
approximately 50% reduction in usable space for boot code. To better utilize this device, the CPCI-810
re-maps the reset vector to FFE0 0100h by inverting memory address 20 (A20) for the first two
processor accesses to memory. These accesses are an absolute jump instruction to the beginning of boot
code. After this jump A20 functions normally. Utilizing this method the majority of the 2 Mbyte Flash
ROM can be used.
2.4
POWERPC MPC603E CORE CACHE, BUFFERS, ARRAYS
The processor core provides independent on-chip, 16-Kbyte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory management units
(MMUs). The MMUs contain 64-entry, two-way set associative, data and instruction lookaside buffers
(TLB) that provide support for demand-paged virtual memory address translation and variable-sized
block translation. The processor also supports block address translation (BAT) arrays of four entries
each.
As an added feature to the MPC603e core, the MPC8240 can lock the contentes of one to three ways in
the instruction and data cache (or the entire cache).
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