HARDWARE
3-2
CPCI-810 User’s Manual
Revision 1.1, June 2001
3.2
FLASH ROM
The CPCI-810 provides 2 Mbytes of sector-programmable Flash ROM for non-volatile code storage.
The Flash ROM is located in local memory space at address FFE0 0000h through FFFF FFFFh. The
mapping ensures that, after a reset, the MPC8240 processor can execute the hard reset exception handler
located at FFF0 0100h.
3.3
CONSOLE SERIAL PORT
A single console serial port with an RS-232 line interface has been included on the CPCI-810. The port
is connected to a RJ-11 style phone jack on the adapter, and can be connected to a host system using the
included phone jack to DB-25 cable (Cyclone P/N 530-2006). The pinout of the console connector is as
shown in Table 3-1.
Table 3-1. Console Port Connector
The serial port is based on a 16C550 UART clocked at 1.843 MHz. The device may be programmed to
use this clock with the internal baud rate counters. The serial port is capable of operating at speeds from
300 to 115200 bps, and can be operated in interrupt-driven or polled mode. The 16C550 register set is
shown in Table 3-2. For a detailed description of the registers and device operation refer to the 16C550
databook.
Table 3-2. UART Register Addresses
Pin
Signal
Description
1
Not Used
2
GND
Ground
3
TXD
Transmit Data
4
RXD
Receive Data
5
Not Used
6
Not Used
Address
Read Register
Write Register
FF00 0000H
Receive Holding Register
Transmit Holding Register
FF00 0008H
Unused
Interrupt Enable Register
FF00 0010H
Interrupt Status Register
FIFO Control Register
FF00 0018H
Unused
Line Control Register
FF00 0020H
Unused
Modem Control Register
FF00 0028H
Line Status Register
Unused
FF00 0030H
Modem Status Register
Unused
FF00 0038H
Scratchpad Register
Scratchpad Register
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