HARDWARE
3-6
CPCI-810 User’s Manual
Revision 1.1, June 2001
3.8.2
Secondary PCI Arbitration
Secondary bus arbitration logic, between the MPC8240 processor, the 21154 bridge, the two ethernet
interfaces and the two PMC devices, is contained within the MPC820. The bus arbitration unit allows
fairness as well as a priority mechanism. A two-level round-robin scheme is used in which each device
can be programmed within a pool of high- or low-priority arbitration. One member of the low-priority
pool is promoted to the high-priority pool. As soon as it is granted the bus it returns to the low-priority
pool.
3.8.3
DMA Channels
The MPC8240 processor features two DMA channels. Data movement occurs on the PCI and/or
memory bus. Each channel has a 64-byte queue to facilitate the gathering and sending of data. Both the
local processor and PCI masters can initiate a DMA transfer. Some of the features of the MPC8240
DMA unit include: misaligned transfer capability, scatter gather DMA chaining and direct DMA
modes, and interrupt on completed segment, chain, and error. Figure 3-5 provides a block diagram of
the MPC8240 DMA unit.
Figure 3-5. MPC8240 Processor DMA Controller
3.8.4
Message Unit
The MPC8240 provides a message unit (MU) to facilitate communications between the host processor
and peripheral processors. The MPC8240’s MU can operate with generic messages and doorbell
registers, and also implements an I
2
O compliant interface.
PCI Interface Unit
Interface Logic
FIFO
FIFO
DMA 1
DMA 0
To memory interface
PCI Bus
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