MPC8240 PROCESSOR
CPCI-810 User’s Manual
2-5
Revision 1.1, June 2001
2.6.3
Error Handling and Exceptions
Errors detected by the MPC8240 are reported to the processor core by asserting an internal machine
check signal (mpc#). The MPC8240 detects illegal transfer types from the processor, illegal Flash write
transactions, PCI address and data parity errors, accesses to memory addresses out of the range of
physical memory, memory parity errors, memory refresh overflow errors, ECC errors, PCI master-abort
cycles, and PCI received target-abort errors. Table 2-4 describes the relative priorities and recoverablity
of externally-generated errors and exceptions.
Table 2-4. Error Priorities
Priority
Exception
Cause
0
Hard reset
Power-on reset, CompactPCI chassis reset switch or via
JTAG controller
1
Machine check
Processor transaction error, or Flash error
2
Machine check
PCI address parity error or PCI data parity error when the
CPCI-810 is acting as the PCI target
3
Machine check
Memory select error, memory refresh overflow, or ECC error
4
Machine check
PCI address parity error or PCI data parity error when the
CPCI-810 is acting as the PCI master, PCI master-abort, or
received PCI target-abort
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