pSOS SOFTWARE DEVELOPMENT
CPCI-810 User’s Manual
4-3
Revision 1.1, June 2001
4.4.1
pSOS PCI Device Driver Interface
Once initialization is complete, a pSOS PCI device list is maintained containing pertinent information
on PCI devices found and configured in the system. Thus, device driver developers can use any of the
functions described in chapter 6 of the pRISM+ Advance Topics Guide to find, claim, or access any
local PCI or CompactPCI devices. In addition, the PCI header file (\pci\pcihdr.h) provides useful
protypes and important macros for dealing with PCI devices.
One important definition in this header file is the PCI_LOC structure, which is used to define the PCI
location of a particular device. This structure is defined below in Figure 4-2. At PCI configuration, a
list of PCI_LOC structures is created by the pSOS Auto-Configuration. This list is defined in pcicfg.c
by:
PCI_LOC pci_dev_list[PCI_DEV_LIST_SIZE];
This list is important, as it contains a PCI_LOC structure for all of the PCI devices on the local PCI bus.
Many pSOS PCI functions, such as those to find a particular device in the list, require a pointer to this
list and the list length as arguments. Others, such as those that access a particular PCI device, require
the PCI_LOC element from the list, which indicates which device the transaction is to occur on.
typedef struct pciloc {
short bus;
/* bus number */
char device;
/* device number */
char function;
/* function number */
char hostBridge;
/* Host/PCI bridge number*/
unsigned char cfgFlags;
/* Configuration flags */
unsigned char claimed;
/* Claimed Status */
unsigned char cfgStat;
/* Configuration Status */
unsigned long dev_vend;
/* Devices and Vendor ID */
unsigned long keyValue;
/* pSOS Key Value */
unsigned long intrVec;
/* Interrupt vector number */
} PCI_LOC;
Figure 4-2. PCI_LOC Structure Definition
For further information on the PCI configuration, consult the Intel 21154 PCI-to-PCI Bridge Data
Sheet, chapter 8 of the MPC8240 User’s Manual, and chapter 6 of the pRISM+ Advance Topics Guide.
4.5
EPIC INTERRUPT PROGRAMMING
The Embedded Programmable Interrupt Controller (EPIC) is the general-purpose interrupt controller
internal to the MPC8240. EPIC control and status registers are located in the EUMB.
CPCI-810 hardware is configured to provide fifteen dedicated external hardware interrupts, which are
time-division multiplexed onto one serial input on the MPC8240. The EPIC controller also provides
four internal timers that can be interrupt sources, and handles internal interrupts from the I
2
C, I
2
O, and 2
DMA channels.
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