HARDWARE
CPCI-810 User’s Manual
3-5
Revision 1.1, June 2001
3.7
LEDS
The CPCI-810 has twelve green LEDs. The four green LEDs labeled, IOP, ACT, STAT0, and STAT1
are under software control. The LEDs are controlled by a write-only register which is located at address
FF20 0000H. The LED Register bitmap is shown in Figure 3-4.
As mentioned previously, two LEDs are provided for the POWERGOOD power supply status and two
LEDs are for fan interrupt status.
The remaining four LEDs are associated with the two ethernet circuits and indicated link integrity and
network activity for each port. Refer to section 3.7.2 for additional information.
Figure 3-4. LED Register Bitmap, FF20 0000H
3.8
PCI INTERFACE
The CPCI-810 contains a primary 64-bit PCI bus and a secondary 32-bit PCI bus. Both buses are
clocked at 33 MHz. The primary PCI bus interfaces the 64-bit CompactPCI bus to the 21154 PCI-to-
PCI bridge. The secondary side of the 21154 interfaces a 32-bit PCI bus to the MPC8240 with the PMC
module and the two ethernet ports.
3.8.1
Primary PCI Arbitration
The primary PCI bus arbitration is provided by the 21154 PCI-to-PCI bridge. The arbiter arbitrates
between the CPCI-810 primary PCI bus requests and the bus requests from the seven peripheral
CompactPCI locations. The arbiter supports a programmable 2-level rotating algorithm. Two groups
of masters are assigned, a high priority group and a low priority group. The low priority group as a
whole represents one entry in the high priority group; that is, if the high priority group consists of n
masters, then in at least every n + 1 transactions the highest priority is assigned to the low priority
group. Priority rotates evenly among the low priority group. In the case of the CPCI-810, the default
grouping, all peripheral slots are assigned to the low priority group and the 21154 is assigned to the high
priority group is maintained.
Activity
Stat0
Stat1
IOP
(write only)
(1) LED on
(0) LED off
7
6
5
4
3
2
1
0
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