AW86225
October 2021 V1.9
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23 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
The master device restarts the data transfer process by continuously generating STOP state and START state
or a separate Repeated START;
Master sends 7-bits address of the slave device and followed by a read / write flag (flag
W
R/
= 1) again;
The slave device asserts an acknowledgment (ACK) bit to confirm whether the register address is correct or
not;
Master transmits 8 bits of data to register which needs to be read;
The slave device sends an acknowledgment bit (ACK) to confirm whether the data is sent successfully;
The device automatically increments register address once after sent each acknowledge bit (ACK),
The master device generates the STOP state to end the data transmission.
START
slave device address
R/W
A
Register address
A
Read data
STOP
A
‘
0
’
(
write
)
From the master to the slave device
From slave to master device
data
transmission
direction
(1)
(2)
(3)
(4)
(5)
(9)
(12)
(10)
(9r)
(10r)
Data Transmission: 8 + 1 bit data acknowledge bit (ACK)
Register address auto increment - (11)
Sr
(6)
slave device address
R/W
‘
1
’
(
read
)
(7)
A
(8)
Read data
A
Sr = repeated START
or Send STOP state before sending START state
Figure 26 Reading process (data transmission direction remains the same)
CHIP ID
CHIPID(2-bit) consists of CHIPID_H and CHIPID_L. The features of CHIPID are shown in the following table.
Table 4 CHIPID feature
CHIPID (0x64)
Product
CHIPID_H
0: AW86223/AW86224/AW86225
1: AW86214
CHIPID_L
0: AW86224/AW86225
1: AW86223/AW86214
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