AWINIC AW86225, Руководство пользователя

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AW86225
October 2021 V1.9
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29 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
7:4 Reserved RW Not used 0
3:0 BRK_GAIN RW Gain factor of brake 8
CONTCFG6: (Address 1Dh)
Bit Symbol R/W Description Default
7 TRACK_EN RW
Track switch:
0: disable
1: enable
1
6:0 DRV1_LVL RW
Level for the first cont drive.
When VBAT_MODE=1:
no load output voltage=6.1*DRV1_LVL/128(V);
if (6.1*DRV1_LVL)/VDD > 128, no load output voltage=VDD;
When VBAT_MODE=0:
no load output voltage=VDD*DRV1_LVL/128(V)
0x7F
CONTCFG7: (Address 1Eh)
Bit Symbol R/W Description Default
7 Reserved RW Not used 0
6:0 DRV2_LVL RW
Level for the second cont drive.
When VBAT_MODE=1:
no load output voltage=6.1*DRV1_LVL/128(V);
if (6.1*DRV1_LVL)/VDD > 128, no load output voltage=VDD;
When VBAT_MODE=0:
no load output voltage=VDD*DRV1_LVL/128(V)
0x50
CONTCFG8: (Address 1Fh)
Bit Symbol R/W Description Default
7:0 DRV1_TIME RW Number of half cycle for the first cont drive 4
CONTCFG9: (Address 20h)
Bit Symbol R/W Description Default
7:0 DRV2_TIME RW Number of half cycle for the second cont drive. 6
CONTCFG10: (Address 21h)
Bit Symbol R/W Description Default
7:0 BRK_TIME RW The number of half cycle of brake mode 8
CONTCFG11: (Address 22h)
Bit Symbol R/W Description Default
7:0 TRACK_MARGIN RW
Margin value of tracking, the smaller margin, the higher tracking accuracy and
the lower loop stability(unit: 1/48K s)
15
CONTRD14: (Address 25h)
Bit Symbol R/W Description Default
7:0 F_LRA_F0_H RO
High 8 bit of the measure value for the f0 of LRA in the f0 detection mode
F0=(384000/(F_LRA_F0_H*256+F_LRA_F0_L))Hz
0
CONTRD15: (Address 26h)
Bit Symbol R/W Description Default
7:0 F_LRA_F0_L RO
Low 8 bit of the measure value for the f0 of LRA in the f0 detection mode
F0=(384000/(F_LRA_F0_H*256+F_LRA_F0_L))Hz
0
CONTRD16: (Address 27h)
Bit Symbol R/W Description Default
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