AWINIC AW86225, Руководство пользователя

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AW86225
October 2021 V1.9
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33 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
1: HDP/HDN output voltage ≥ 124/128*VDD maintains (PRCTIME/3k)s,
HDP/HDN is pulled down protectively
6:0 PRCTIME RW
Set protection time of output signal protection mode of pwm, unit time is (1/3k)
s.
0x20
PWMCFG2: (Address 4Dh)
Bit Symbol R/W Description Default
7:5 Reserved RW Not used 1
4 PD_HWM RW
shutdown half wave modulate
0: half wave mode
1: full wave mode
0
3:0 Reserved RW Not used 8
PWMCFG3: (Address 4Eh)
Bit Symbol R/W Description Default
7 PR_EN RW
Set enable of input signal protection mode of pwm:
0: disable
1: HDP/HDN output voltage >= PRLVL/128*VDD maintains (PRTIME/3k)s,
HDP/HDN is pulled down protectively
1
6:0 PRLVL RW Set protection voltage of output signal protection mode of pwm 0x3F
PWMCFG4: (Address 4Fh)
Bit Symbol R/W Description Default
7:0 PRTIME RW
Set protection time of input signal protection mode of pwm, unit time is (1/3k)
s.
0x32
DETCFG1: (Address 51h)
Bit Symbol R/W Description Default
7:5 Reserved RW Not used 0
4 RL_OS RW
Set diagnostic mode
0:disable
1:RL
0
3 Reserved RW Not used 0
2:0 CLK_ADC RW
Set frequency of ADC clock
b000: 12MHz
b001: 6MHz
b010: 3MHz
b011: 1.5MHz
b100: 0.75MHz
b101: 0.375MHz
b110: 0.1875MHz
b111: 0.09375MHz
2
DETCFG2: (Address 52h)
Bit Symbol R/W Description Default
7:2 Reserved RW Not used 0
1 VBAT_GO RW Set the enabled of VBAT mode 0
0 DIAG_GO RW Set the enabled of DIAG mode 0
DET_RL: (Address 53h)
Bit Symbol R/W Description Default
7:0 RL RO
The measured value of resistance of LRA in DIAG mode(high eight bits)
RL=((RL*4+RL_LO)*678)/(1024*d2s_gain)Ω
0
DET_VBAT: (Address 55h)
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