AWINIC AW86225, Руководство пользователя

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AW86225
October 2021 V1.9
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30 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
7:0 CONT_F0_H RO
The measure value for the f0 of LRA in the continuous detection mode(high
eight bits)
F0=(384000/(CONT_F0_H*256+CONT_F0_L))Hz
0
CONTRD17: (Address 28h)
Bit Symbol R/W Description Default
7:0 CONT_F0_L RO
The measure value for the f0 of LRA in the continuous detection mode(low eight
bits)
F0=(384000/(CONT_F0_H*256+CONT_F0_L))Hz
0
RTPCFG1: (Address 2Dh)
Bit Symbol R/W Description Default
7:4 Reserved RW Not used 3
3:0 BASE_ADDR_H RW
High four bits of start address of wave SRAM
BASE_ADDR = BASE_ADDR_H * 256 + BASE_ADDR_L
0x08
RTPCFG2: (Address 2Eh)
Bit Symbol R/W Description Default
7:0 BASE_ADDR_L RW
Low eight bits of start address of wave SRAM
BASE_ADDR = BASE_ADDR_H * 256 + BASE_ADDR_L
0
RTPCFG3: (Address 2Fh)
Bit Symbol R/W Description Default
7:4 FIFO_AEH RW
High four bits of RTP FIFO almost empty threshold
FIFO_AE = FIFO_AEH * 256 + FIFO_AEL
0x02
3:0 FIFO_AFH RW
High four bits of RTP FIFO almost full threshold
FIFO_AF = FIFO_AFH * 256 + FIFO_AFL
0x06
RTPCFG4: (Address 30h)
Bit Symbol R/W Description Default
7:0 FIFO_AEL RW
Low eight bits of RTP FIFO almost empty threshold
FIFO_AE = FIFO_AEH * 256 + FIFO_AEL
0x00
RTPCFG5: (Address 31h)
Bit Symbol R/W Description Default
7:0 FIFO_AFL RW
Low eight bits of RTP FIFO almost full threshold
FIFO_AF = FIFO_AFH * 256 + FIFO_AFL
0x00
RTPDATA: (Address 32h)
Bit Symbol R/W Description Default
7:0 RTP_DATA RW
RTP mode , data write entry, when data written into this register, the data will
be written into RTP FIFO
0
TRGCFG1: (Address 33h)
Bit Symbol R/W Description Default
7 TRG1_POS RW
TRG1 rising edge enable/disable control
0: disable
1: enable
0
6:0 TRG1SEQ_P RW TRIG1 posedge trigged wave sequence number 1
TRGCFG4: (Address 36h)
Bit Symbol R/W Description Default
7 TRG1_NEG RW
TRG1 falling edge enable/disable control
0: disable
1: enable
0
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