AW86225
October 2021 V1.9
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7 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
VDD=4.2V
I
2
C Interface Timing
Parameter
fast mode
fast mode plus
UNIT
No.
Symbol
Name
MIN
TYP
MAX
MIN
TYP
MAX
1
f
SCL
SCL Clock frequency
400
1000
kHz
2
t
LOW
SCL Low level Duration
1.3
0.5
μs
3
t
HIGH
SCL High level Duration
0.6
0.26
μs
4
t
RISE
SCL, SDA rise time
0.3
0.12
μs
5
t
FALL
SCL, SDA fall time
0.3
0.12
μs
6
t
SU:STA
Setup time SCL to START state
0.6
0.26
μs
7
t
HD:STA
(Repeat-start) Start condition hold time
0.6
0.26
μs
8
t
SU:STO
Stop condition setup time
0.6
0.26
μs
9
t
BUF
the Bus idle time START state to STOP
state
1.3
0.5
μs
10
t
SU:DAT
SDA setup time
0.1
0.1
μs
11
t
HD:DAT
SDA hold time
10
10
ns
SCL
SDA
t
HI GH
t
LOW
t
SU:DAT
t
HD:DAT
t
RI SE
t
FALL
(2)
(3)
(4)
(5)
(10)
(11)
Figure 4 SCL and SDA timing relationships in the data transmission process
SCL
SDA
t
SU:STA
t
HD:STA
(6)
(7)
t
SU:STO
(8)
t
BUF
(9)
Figure 5 The timing relationship between START and STOP state
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