AW86225
October 2021 V1.9
www.awinic.com
32 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
RAMADDRL: (Address 41h)
Bit
Symbol
R/W
Description
Default
7:0
RAMADDRL
RW
SRAM address low eight bits
0
RAMDATA: (Address 42h)
Bit
Symbol
R/W
Description
Default
7:0
RAMDATA
RW
SRAM data entry
0
SYSCTRL1: (Address 43h)
Bit
Symbol
R/W
Description
Default
7
VBAT_MODE
RW
VDD adjust mode:
0: software adjust mode
1: hardware adjust mode
0
6:4
Reserved
RW
Not used
0
3
EN_RAMINIT
RW
Enable clock:
1: open the digital module clock
0: close the digital module clock
0
2
EN_FIR
RW
Set enable of FIR filter
1
1:0
Reserved
RW
Not used
0
SYSCTRL2: (Address 44h)
Bit
Symbol
R/W
Description
Default
7
WAKE
RW
Chip enable control
1: force the chip to enter active mode
0
6
STANDBY
RW
Chip disable control:
1: force the chip to enter standby mode
0
5:4
Reserved
RW
Not used
2
3
INTN_PIN
RW
Multi-mode PIN control:
0: INTN/TRIG used as TRIG1
1: INTN/TRIG used as INTN
1
2
Reserved
RW
Not used
0
1:0
WAVDAT_MODE
RW
Waveform data sample rate selection:
b00: 24Khz
b01: 48kHz
others: 12KHz rate
0
SYSCTRL7: (Address 49h)
Bit
Symbol
R/W
Description
Default
7
Reserved
RW
Not used
0
6
GAIN_BYPASS
RW
0: gain cannot be changed when playing
1: gain can be changed when playing
0
5:3
Reserved
RW
Not used
2
2:0
D2S_GAIN
RW
Set D2S gain:
b000: 1
b001: 2
b010: 4
b011: 5
b100: 8
b101: 10
b110: 20
b111: 40
4
PWMCFG1: (Address 4Ch)
Bit
Symbol
R/W
Description
Default
7
PRC_EN
RW
Set enable of output signal protection mode of pwm:
0: disable
1
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