AW86225
October 2021 V1.9
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21 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
General I
2
C Operation
The I
2
C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in
a system. The device is addressed by a unique 7-bit address; the same device can send and receive data. In
addition, Communications equipment has distinguished master from slave device: In the communication
process, only the master device can initiate a transfer and terminate data and generate a corresponding clock
signal. The devices using the address access during transmission can be seen as a slave device.
SDA and SCL connect to the power supply through the current source or pull-up resistor. SDA and SCL default
is a high level. There is no limit on the number of bytes that can be transmitted between start and stop
conditions. When the last word transfers, the master generates a stop condition to release the bus.
START state: The SCL maintain a high level, SDA from high to low level
STOP state: The SCL maintain a high level, SDA pulled low to high level
Start and Stop states can be only generated by the master device. In addition, if the device does not produce
STOP state after the data transmission is completed, instead re-generate a START state (Repeated START,
Sr), and it is believed that this bus is still in the process of data transmission. Functionally, Sr state and START
state is the same. As shown in Figure 22.
START
(S)
SDA
SCL
STOP
(P)
Figure 22 START and STOP state generation process
In the data transmission process, when the clock line SCL maintains a high level, the data line SDA must
remain the same. Only when the SCL maintain a low level, the data line SDA can be changed, as shown in
Figure 23. Each transmission of information on the SDA is 9 bits as a unit. The first eight bits are the data to
be transmitted, and the first one is the most significant bit (Most Significant Bit, MSB), the ninth bit is an
confirmation bit (Acknowledge, ACK or A ), as shown in Figure 24. When the SDA transmits a low level in ninth
clock pulse, it means the acknowledgment bit is 1, namely the current transmission of 8 bits’ data is confirmed,
otherwise it means that the data transmission has not been confirmed. Any amount of data can be transferred
between START and STOP state.
SDA
SCL
Data cable
Remains the same:
At this point the
data is valid
Data transmission:
In this case the data
is invalid
Figure 23 The data transfer rules on the I
2
C bus
The whole process of actual data transmission is shown in Figure 24. When generating a START condition,
the master device sends an 8-bit data, including a 7-bit slave addresses (Slave Address), and followed by a
"read / write" flag (
W
R/
). The flag is used to specify the direction of transmission of subsequent data. The
master device will produce the STOP state to end the process after the data transmission is completed.
However, if the master device intends to continue data transmission, you can directly send a Repeated
START state, without the need to use the STOP state to end transmission.
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