AW86225
October 2021 V1.9
www.awinic.com
31 Copyright © 2020 SHANGHAI AWINIC TECHNOLOGY CO., LTD
6:0
TRG1SEQ_N
RW
TRIG1 negedge trigged wave sequence number
1
TRGCFG7: (Address 39h)
Bit
Symbol
R/W
Description
Default
7
TRG1_POLAR
RW
TRIG1 pin active polarity, when host supply positive level, this bit set to 0, else
set to 1
0
6
TRG1_LEV
RW
TRG1 mode control
0: edge
1: level
0
5
TRG1_BRK
RW
When set 1, enable auto brake after TRG1 playback mode is stopped
1
4:0
Reserved
RW
Not used
2
TRGCFG8: (Address 3Ah)
Bit
Symbol
R/W
Description
Default
7:5
Reserved
RW
Not used
1
4:3
TRG1_MODE
RW
TRIG pin playback mode selection
b00: PWM_LRA mode
b00: PWM_ERM mode
b10: TRIG mode
b11: None
This product does not support PWM_LRA and PM_ERM modes, users must
configure this register as TRIG mode after powering on
0
2
TRG1_STOP
RW
When set 1, TRG1 playback mode can be stopped immediately
0
1:0
Reserved
RW
Not used
0
GLBVFG2: (Address 3Ch)
Bit
Symbol
R/W
Description
Default
7:0
START_DLY
RW
Startup delay time, unit time is (1/48k)s
4
GLBCFG4: (Address 3Eh)
Bit
Symbol
R/W
Description
Default
7:6
GO_PRIO
RW
Priority value of GO TRIG
High priority can interrupt the playback of low priority, and low priority cannot
interrupt the playback of high priority. When the priority settings are consistent,
the default priority will be implemented
0
5:2
Reserved
RW
Not used
6
1:0
TRG1_PRIO
RW
Priority value of TRIG1 pin
High priority can interrupt the playback of low priority, and low priority cannot
interrupt the playback of high priority. When the priority settings are consistent,
the default priority will be implemented
3
GLBRD5: (Address 3Fh)
Bit
Symbol
R/W
Description
Default
7:4
Reserved
RO
Not used
0
3:0
GLB_STATE
RO
The state of glb state
b0000: STANDBY
b0110: CONT
b0111: RAM
b1000: RTP
b1001: TRIG
b1011: BRAKE
0
RAMADDRH: (Address 40h)
Bit
Symbol
R/W
Description
Default
7:4
Reserved
RW
Not used
0
3:0
RAMADDRH
RW
SRAM address high 4 bits
0
awinic Confidential
