VMEbus Slave Interface
6-19
if (noError < 0){
exit();
}
/*At this point the Universe should be mapped to its base
address in PCI MEM space - i.e. it’s now available as a normal
memory-mapped PCI device*/
/*Let’s first clean up the SYSFAIL line - it’s asserted after power
up until otherwise noted*/
universeIO->VCSR_CLR |= ES((int)UNIV_VCSR_SYSFAIL);
/*Configure the Universe VME arbitration parameters*/
universeIO->MAST_CTL = ES((int)(UNIV_MAST_CTL_MAXRTRY_FOREVER |
UNIV_MAST_CTL_PWON_128B |
UNIV_MAST_CTL_VRL_L3 |
UNIV_MAST_CTL_VRM_DEMAND |
UNIV_MAST_CTL_VREL_ROR |
UNIV_MAST_CTL_PABS_32B));
/*We are going to define one massive window which consists purely
of A32/D32 space: this is our PPC->PCI->VME path*/
/*First assure that the window is disabled before we make any
modifications to its setup. Otherwise erratic behavior could result*/
universeIO->LSI0_CTL &= ES((int)(~UNIV_LSIX_CTL_EN));
/*LSI0_BS contains the base address of our window, as seen by the
processor*/
universeIO->LSI0_BS = ES((int)CHRP_PCI_MEM_SPACE_START);
/*LSI0_BD contains the end of our window as seen by the processor*/
universeIO->LSI0_BD = ES((int)CHRP_PCI_MEM_SPACE_END_VME);
/*LSI0_TO contains the "translation offset" which is effectively added to
the working window address, if necessary*/
universeIO->LSI0_TO = ES((int)CHRP_PCI_VME_LSI0_TO);
/*now setup the attributes of this window using LSI0_CTL*/
universeIO->LSI0_CTL = ES((int)(UNIV_LSIX_CTL_VAS_A32 |
UNIV_LSIX_CTL_PGM_DATA |
UNIV_LSIX_CTL_SUPER |
UNIV_LSIX_CTL_VDW_64 |
UNIV_LSIX_CTL_LAS_MEM));
/*Enable the window*/
universeIO->LSI0_CTL |= ES((int)(UNIV_LSIX_CTL_EN));
/*Map the VME->PCI window - a32, into PCI mem space - note that this is a
big uniform window. For now, no other modes are enabled (a24 etc)*/
/*VSI0_BS = base address of the window as seen on the VME bus*/
universeIO->VSI0_BS = ES((int)VME_SLAVE_ADDR_START & 0xFFFFF000);
/*VSI0_BD = end of the VME window. BD-BS = size*/
universeIO->VSI0_BD = ES((int)VME_SLAVE_ADDR_END & 0xFFFFF000);
Содержание BajaPPC-750
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Страница 16: ...0002M621 15 ix Register Map 9 1 Counter Timer Status CTSR 9 2 Register Map 9 2 Counter Timer Mode CTMR 9 4...
Страница 19: ...xii BajaPPC 750 Contents...
Страница 57: ...3 12 BajaPPC 750 Central Processing Unit May 2002...
Страница 77: ...5 12 BajaPPC 750 PMC PCI Interface May 2002...
Страница 111: ...6 34 BajaPPC 750 VMEbus Interface May 2002...
Страница 135: ...8 18 BajaPPC 750 Serial and Parallel I O May 2002...
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