Artesyn BajaPPC-750, Руководство пользователя

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Cache Memory 3-9
0002M621-15
3.6.1 Integrated Level 2 Cache
In addition to the on-chip caches, the PPC750 CPU utilizes a 1-megabyte,
integrated secondary cache provided by two synchronous random access mem-
ory (SRAM) chips. For the BajaPPC-750, the cache operates in Fast L2 mode and
integrates data, tag, host interface, and LRU memory with a cache controller. At
122 MHz and above, it performs with zero wait states (2-1-1-1 burst). The cache
design is two-way, set-associative and employs LRU logic.
The software can read an 8-bit register at FF98,0030
16
to determine the L2 config-
uration settings (see Register Map 3-6). There are various configuration resistors
that set the bit values for this register (0=installed, 1=not installed). Please refer to
the IBM documentation for details on the L2 configuration parameters.
7 6 5 4 3 2 1 0
L2 DIVISOR HLD DLL J2X J1X
Register Map 3-6. BajaPPC-750 L2 Cache/PMC Bus Mode
L2 L2 cache enable/disable. 0=enabled, 1=disabled
DIVISOR L2 clock divisor. 00=divide by 3, 01=divide by 2.5, 10=divide by 2,
11=divide by 1.5
HLD L2 hold time. 00=0.5 nanosecond, 01=1 nanosecond, 10=1.2 nanosec-
onds, 11=1.5 nanoseconds
DLL L2 DLL speed. 0=fast, 1=slow
J2X–J1X PMC bus mode. These bits do not affect the L2 cache. Refer to page 3 for
details on the PMC bus mode.