Artesyn BajaPPC-750, Руководство пользователя

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4-2 BajaPPC-750: On-Card Memory Configuration
May 2002
The BajaPPC-750 Configuration Address and Data Registers at FEC0,0000
16
and
FEE0,0000
16
allow access to the MPC106 registers. To initiate an access, write the
value 0x8000,00 nn (where nn is the MPC106 address of the register you want to
access) to the Configuration Address Register at FEC0,0000
16
. The data for that
register then may be read from or written to the Configuration Data Register at
FEE0,0000
16
.
4.2 Boot Memory Configuration
The BajaPPC-750 has a 32-pin PLCC socket for either a byte-wide EPROM (up to
512 kilobytes) or a 512-kilobyte flash memory chip. This socketed memory occu-
pies physical address space FF90,0000-FF97,FFFF
16
.
CAUTION. When removing socketed PLCC devices, always use an extrac-
tion tool designed specifically for that task. Otherwise, you
risk damaging the PLCC device.
Jumpers on the BajaPPC-750 circuit board configure the memory as shown in
Table 4-2. The on-board monitor (HKMON) is standard in the first 512K of this
flash memory space.
The MPC106 controls the access time for ROM. The default power-up timing
allows boards of any speed to work with ROMs of speeds faster than 150 nanosec-
onds. We strongly suggest that you use the default timing because of the inherent
risks of optimizing timing for a specific configuration and because the ROM is
cached.
Table 4-2. Memory Configuration Jumpers
Jumper
a
a.
Spare jumpers are located at JP2 (board revs. 1 and 21 only).
Function Options Default Configuration
JP4 Selects type of memory in
PLCC socket. JP4 in, Flash.
JP4 out, EPROM.
Varies
JP5 Enables writing to Flash
memory in PLCC socket JP5 in, Enable flash write.
JP5 out, Disable flash write. JP5 in,
Enable write
JP6 Selects boot device JP6 in, User Flash Bank 0
JP6 out, PLCC socket. JP6 in, User
Flash Bank 0t