Artesyn BajaPPC-750, Руководство пользователя

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6-14 BajaPPC-750: VMEbus Interface
May 2002
and VSI4 register sets, which have a 4-kilobyte resolution. Since the bit assign-
ments are similar for all eight VMEbus slave images, only image 0 will be dis-
cussed here. Refer to the
Universe User’s Manual for additional details.
The VMEbus Slave Image 0 Base Address Register, VSI0_BS, at hex offset F04
16
defines the lowest address in the range to be decoded. Bits BS[31:12] hold the
base address, and bits [11:0] are reserved.
The VMEbus Slave Image 0 Bound Address Register, VSI0_BD, at hex offset F08
16
defines the window size for the slave image. Bits BD[31:12] hold the bound
address, and bits [11:0] are reserved.
NOTE. Since the MPC106 memory controller currently issues a retry upon
detecting a memory select error, the maximum slave window size
should be limited to the size of the desired memory-mapped region.
The slave window can make any portion of the BajaPPC-750 memory
map available on the VMEbus.
The VMEbus Slave Image 0 Control Register, VSI0_CTL, at hex offset F00
16
defines
general VMEbus and PCI bus controls for this image. The PCI master interface
must be enabled before a VMEbus slave image can respond to an incoming cycle
(see BM bit description and Register Map 6-2).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN PWEN PREN Reserved PGM SUPER Reserved VAS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved LD64EN LLRMW Reserved LAS
Register Map 6-6. Universe VME Slave Image 0 Control, VSI0_CTL
EN Enable the image. (Disable when configuring).
Binary 0=disabled, 1=enabled.
PWEN Posted write enable.
Binary 0=disabled, 1=enabled.
PREN Pre-fetch read enable.
Binary 0=disabled, 1=enabled.
PGM Program/data AM code.
Binary 00=reserved, 01=data, 10=program, 11=both.