Artesyn BajaPPC-750, Руководство пользователя

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8-12 BajaPPC-750: Serial and Parallel I/O
May 2002
8.3.3 Programmable Baud Rate
The Ultra I/O controller has a programmable baud rate generator that works in
conjunction with the two 8-bit Divisor Latch registers, DLL and DLM. The baud
rate generator can divide the clock input by a number from 1 to 65535, which is
stored as a 16-bit binary value in the DLL and DLM registers. The resulting clock
output frequency is 16 times the baud rate.
Upon initialization of the DLL and DLM registers, the value of the divisor deter-
mines the clock as follows:
0 = clock divided by 3
1 = inverse of input oscillator
2 = clock divided by 2, 50% duty cycle
3 or greater = low for 2 bits, high for count remainder
Table 8-6. Baud Rate Divisors (1.8462 MHz Crystal)
Desired
Baud Rate Divisor for
16x Clock Clock Input
(MHz) Percentage of
Error
50 2304 1.8462 .001
75 1536 1.8462 .2
110 1047 1.8462 .2
134.5 857 1.8462 .004
150 768 1.8462 .2
300 384 1.8462 .2
600 192 1.8462 .2
1200 96 1.8462 .2
1800 64 1.8462 .2
2000 58 1.8462 .005
2400 48 1.8462 .2
3600 32 1.8462 .2
4800 24 1.8462 .2
7200 16 1.8462 .2
9600 12 1.8462 .2
19200 6 1.8462 .2
38400 3 1.8462 .030
57600 2 1.8462 .16
115200 1 1.8432 .16
230400 32770 3.6864 .16
460800 32769 7.3728 .16