Artesyn BajaPPC-750, Руководство пользователя

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VMEbus Slave Interface 6-17
0002M621-15
6.3.2 Data Transfers
The Universe has a software-configurable, high-performance, internal DMA con-
troller to facilitate data transfers between the PCI bus and VMEbus. It uses a sin-
gle bidirectional FIFO to decouple DMA operations between the busses. The DMA
controller supports a linked-list mode, where it can perform multiple block trans-
fers by following pointers in the list. Please refer to Section 2.8 in the
Universe
User’s Manual for a thorough explanation of the DMA controller.
Generally, if the width of the PCI bus data is less than that of the VMEbus, no
packing or unpacking occurs between the two busses. However, for 32-bit PCI
multi-data beat transactions to a PCI slave image with a 64-bit VMEbus data
width, packing or unpacking does occur to maximize the full bandwidth on both
busses. The Universe only generates aligned VMEbus transactions; so if the PCI
data beat has non-contiguous byte enables, it is divided into multiple aligned
VMEbus transactions. The initiating PCI image or PWON field of the MAST_CTL
register (see Register Map 6-3) determines the length of BLT/MBLT cycles. The
Universe will attempt block DMA transfers of up to 256 bytes for BLT and 2 kilo-
bytes for MBLT as limited by the VMEbus specification (and VON counter).
CAUTION. Do not perform any byte-, word-, or longword-wide reads/
writes on the VMEbus while a DMA transaction is pending on
a BajaPPC-750 that utilizes revision Z1 of the Universe chip. If
another VME master attempts a single-beat slave transaction
(byte-, word-, or longword-wide read/write) under this condi-
tion, the slave transaction following the single-beat slave
transaction will occur at a corrupted address. For the latest
information regarding Universe errata, please visit the Tundra
web site (see Section 1.4.3).
6.4 VMEbus Slave Interface
When one of the eight programmed slave or register images is accessed by a VME-
bus master, the Universe becomes a slave. It handles incoming write transactions
from the VMEbus as either coupled-writes or posted-writes, as determined by the
VMEbus slave image. (Refer to control registers in Section 6.2.) For posted-writes,
a FIFO receives the data an acknowledgment is sent to the VMEbus master. For
coupled-writes, the VMEbus master receives and acknowledgment only when the
transaction is complete on the PCI bus. Similarly, read transactions may be either
pre-fetched or coupled.