I/O Controller
8-5
8.2.1 Block Addressing
The CPU accesses the Ultra I/O controller through a series of read/write registers,
which have configurable base addresses. All of the I/O registers are 8 bits wide
with the exception of a 16-bit IDE data register at port 1F0
16
.The following table
summarizes the I/O port addressing scheme:
8.2.2 Configuration
Upon reset or power-up, the BIOS uses two configuration ports, INDEX and
DATA, to initialize the logical devices at POST. These ports are only valid when
the Ultra I/O controller is in Configuration mode, as set by the SYSOPT hardware
pin. To enter the configuration state, write 55,55
16
to the CONFIG PORT at
0370
16
. To exit the configuration state, write AA
16
to the same location. Table 8-4
summarizes the Ultra I/O configuration registers. For a complete description of all
the control bits, please refer to the SMC Ultra FDC37C93x user’s documentation.
Table 8-3. Ultra I/O Block Addressing
Hex Base
Address
I/O Block
Logical Device
Base + (0-5) and + (7)
Floppy Disk
0
FE00,0100
Base + (0-7)
Serial Port Com 1
4
FE00,0108
Base + (0-7)
Serial Port Com 2
5
FE00,0110
Base + (0-3)
Base + (0-7)
Base + (0-3), + (400-402)
Base + (0-7), + (400-402)
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
3
Base1 + (0-7), Base2 + (0)
IDE1
1
Base1 + (0-7), Base2 + (0)
IDE2
2
Table 8-4. Ultra I/O Configuration Registers
Hex Index
Access
Hard Reset
Soft Reset
Register Name
Global Configuration Registers
02
W
00
00
Config. Control
03
R/W
03
n/a
Index Address
07
R/W
00
00
Logical Device Number
20
R
02
02
Device ID - hard wired
21
R
01
01
Device Rev. - hard wired
22
R/W
00
00
Power Control
23
R/W
00
n/a
Power Management
24
R/W
04
n/a
OSC
2D
R/W
n/a
n/a
TEST 1
2E
R/W
n/a
n/a
TEST 2
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