Analog Devices ADSP-BF53x Blackfin, Справочник

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 1-5
Introduction
common address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/performance
balance of some very fast, low latency on-chip memory as cache or SRAM,
and larger, lower cost and lower performance off-chip memory systems.
The L1 memory system is the primary highest performance memory avail-
able to the core. The off-chip memory system, accessed through the
External Bus Interface Unit (EBIU), provides expansion with SDRAM,
flash memory, and SRAM, optionally accessing up to 132M bytes of phys-
ical memory.
The memory DMA controller provides high bandwidth data movement
capability. It can perform block transfers of code or data between the
internal memory and the external memory spaces.
Internal Memory
At a minimum, each Blackfin processors has three blocks of on-chip mem-
ory that provide high bandwidth access to the core:
• L1 instruction memory, consisting of SRAM and a 4-way set-asso-
ciative cache. This memory is accessed at full processor speed.
• L1 data memory, consisting of SRAM and/or a 2-way set-associa-
tive cache. This memory block is accessed at full processor speed.
• L1 scratchpad RAM, which runs at the same speed as the L1 mem-
ories but is only accessible as data SRAM and cannot be configured
as cache memory.
In addition, some Blackfin processors share a low latency, high bandwidth
on-chip Level 2 (L2) memory. It forms an on-chip memory hierarchy with
L1 memory and provides much more capacity than L1 memory, but the
latency is higher. The on-chip L2 memory is SRAM and cannot be config-
ured as cache. On-chip L2 memory is capable of storing both instructions
and data and is accessible by both cores.