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Data Test Registers
6-38 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Data Cache Invalidation
Besides the
FLUSHINV
instruction, explained in the previous section, two
additional methods are available to invalidate the data cache when flush-
ing is not required. The first technique directly invalidates Valid bits by
setting the Invalid bit of each cache line to the invalid state. To implement
this technique, additional MMRs (
DTEST_COMMAND
and
DTEST_DATA[1:0]
)
are available to allow arbitrary reads/writes of all the cache entries directly.
This method is explained in the next section.
For invalidating the complete data cache, a second method is available. By
clearing the
DMC[1:0]
bits in the
DMEM_CONTROL
register (see Figure 6-9,
“L1 Data Memory Control Register,” on page 6-25 ), all Valid bits in the
data cache are set to the invalid state. A second write to the
DMEM_CONTROL
register to set the
DMC[1:0]
bits to their previous state then configures the
data memory back to its previous cache/SRAM configuration. An
SSYNC
instruction should be run before invalidating the cache and a
CSYNC
instruction should be inserted after each of these operations.
Data Test Registers
Like L1 Instruction Memory, L1 Data Memory contains additional
MMRs to allow arbitrary reads/writes of all cache entries directly. The reg-
isters provide a mechanism for data cache test, initialization, and debug.
When the Data Test Command register (
DTEST_COMMAND
) is written to, the
L1 cache data or tag arrays are accessed and data is transferred through the
Data Test Data registers (
DTEST_DATA[1:0]
). The
DTEST_DATA[1:0]
regis-
ters contain the 64-bit data to be written, or they contain the destination
for the 64-bit data read. The lower 32 bits are stored in the
DTEST_DATA[0]
register and the upper 32 bits are stored in the
DTEST_DATA[1]
register.
When the tag arrays are being accessed, then the
DTEST_DATA[0
] register is
used.
L
A
CSYNC
instruction is required after writing the
DTEST_COMMAND
MMR.