Analog Devices ADSP-BF53x Blackfin, Справочник

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On-chip Level 2 (L2) Memory
6-44 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Latency
When cache is enabled, the bus between the core and L2 memory is fully
pipelined for contiguous burst transfers. The cache line fill from on-chip
memory behaves the same for instruction and data fetches. Operations
that miss the cache trigger a cache line replacement. This replacement fills
one 256-bit (32-byte) line with four 64-bit reads. Under this condition,
the L1 cache line fills from the L2 SRAM in
9+2+2+2=15
core cycles. In
other words, after nine core cycles, the first 64-bit (8-byte) fill is available
for the processor.
Figure 6-16 on page 6-44 shows an example of L2
latency with cache on.
In this example, at the end of 15 core cycles, 32 bytes of instructions or
data have been brought into cache and are available to the sequencer. If all
the instructions contain 16 bits, sixteen instructions are brought into
cache at the end of 15 core cycles. In addition, the first instruction that is
Figure 6-16. L2 Latency With Cache On
64 BITS
E F G H
I J
K L
M
N O P
A B C D
A B C
D
E F G H A B C D
INSTRUCTION ALIGNMENT UNIT
T+9 ABCD READY
TO EXECUTE
T+11 EFGH READY
TO EXECUTE
T+13 IJKL READY
TO EXECUTE
T+15 MNOP READY
TO EXECUTE
T+10 A EXECUTES
T+11 B EXECUTES
T+12 C EXECUTES
T+13 D EXECUTES
L2 MEMORY
T+15 F EXECUTES
T+14 E EXECUTES
E F G H
I
J K L
INSTRUCTION ALIGNMENT UNIT
NOTE: AFTER F EXECUTES, GHIJKLMNOP
EXECUTE ON CONSECUTIVE CYCLES.
AFTER P IS IN PIPELINE,
NEW CACHE LINE FILL IS INITIATED.
CYCLES
64 BITS 64 BITS 64 BITS
T+9 T+11 T+15 T+13
EACH INSTRUCTION FETCH IS 32 BYTES
INSTRUCTION ALIGNMENT UNIT