Analog Devices ADSP-BF53x Blackfin, Справочник

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 6-43
Memory
On-chip Level 2 (L2) Memory
Some Blackfin processors provide additional low-latency and high-band-
width SRAM on chip, called Level 2 (L2) memory. L2 memory runs at
CCLK
clock rate, but takes multiple
CCLK
cycles to access.
Simultaneous access to the multibanked, on-chip L2 memory architecture
from the core(s) and system DMA can occur in parallel, provided that
they access different banks. A fixed-priority arbitration scheme resolves
conflicts. The on-chip system DMA controllers share a dedicated 32-bit
data path into the L2 memory system. This interface operates at the
SCLK
frequency. Dedicated L2 access from the processor core is also supported.
Derivatives with on-chip L2 memory provide not only the plain memory
itself. They also provide proper bus and DMA infrastructure. Wide buses
between L1 and L2 memory guarantee high data throughput. A dedicated
DMA controller, called IMDMA, supports data exchange between inter-
nal memories.
The cores and IMDMA share a dedicated, low latency, 64-bit data path
into the L2 SRAM memory. At a core clock frequency of 600 MHz, the
peak data transfer rate across this interface is 4.8 GB/second.
On-chip L2 Bank Access
Two L2 access ports, a processor core port and a system port, are provided
to allow concurrent access to the L2 memory, provided that the two ports
access different memory sub-banks. If simultaneous access to the same
memory sub-bank is attempted, collision detection logic in the L2 pro-
vides arbitration. This is a fixed priority arbiter; the DMA port always has
the highest priority, unless the core is granted access to the sub-bank for a
burst transfer. In this case, the L2 finishes the burst transfer before the sys-
tem bus is granted access.