Analog Devices ADSP-BF53x Blackfin, Справочник

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 6-29
Memory
L1 Data Cache
For definitions of cache terminology, see “Terminology” on page 6-74 .
Unlike instruction cache, which is 4-Way set associative, data cache is
2-Way set associative. When two banks are available and enabled as cache,
additional sets rather than Ways are created. When both Data Bank A and
Data Bank B have memory serving as cache, the
DCBS
bit in the
DMEM_CONTROL
register may be used to control which half of all address
space is handled by which bank of cache memory. The
DCBS
bit selects
either address bit 14 or 23 to steer traffic between the cache banks. This
provides some control over which addresses alias into the same set. It may
therefore be used to affect which addresses tend to remain resident in
cache by avoiding victimization of repetitively used sets.
Accesses to cache do not collide unless they are to the same 4K byte sub-
bank, the same half bank, and to the same bank. Cache has less apparent
multi-ported behavior than SRAM due to the overhead in maintaining
tags. When cache addresses collide, access is granted first to the
DTEST
reg-
ister accesses, then to the store buffer, and finally to cache fill/victim
traffic.
Three different cache modes are available.
• Write-through with cache line allocation only on reads
• Write-through with cache line allocation on both reads and writes
• Write-back which allocates cache lines on both reads and writes
Cache mode is selected by the
DCPLB
descriptors (see “Memory Protection
and Properties” on page 6-45 ). Any combination of these cache modes can
be used simultaneously since cache mode is selectable for each memory
page independently.