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English URL
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E2960A
E2960B
E2960 Series for PCI Express 1.0 and 2.0 (cont.)
System and Protocol Test
Data Link Layer
• Fully implemented data link control and management state machine
• Automatic flow control initialization; programmable credits and flow
control update rate
• Automated generation of data link layer packets (DLLPs): ACK/NAK,
Init/Update-FC
• Automatic generation and checking of LCRC and sequence numbers;
allows the insertion of incorrect LCRCs into TLPs for testing purposes;
automatic retry management
Transaction Layer
• User software can define arbitrary sequences of transactions
• “Send single packet” for simple packet transmission one memory for
block transactions per virtual channel
– Full support for two virtual channels (VCs)
– Conditional start on RX pattern matcher, external trigger in and
completion status
– Generation and receiving of packets at maximum band width
(stress testing) up link width x8 at 5 GT/s Infinite loop
• 1 completer queue defines the way completion packets are sent out
(e.g., lengths, errors inserted, partitioning, etc)
– Completions can be split into individual packets
• Up to 32 outstanding requests can be “pending” (256 in extended
mode) – request without completion
• Decoders (6 BARS + Expansion ROM decoder)
• Payload generation and reception from/into data memory
Error Generation and Analysis Features
Error insertion capabilities on the physical layer, data link layer and
transaction layer
Physical Layer
• Transmitter polarity inversion
• Transmitter lane reversal
• Deterministic lane skew up to 7 symbols
• Link width and lane sequence negotiation emulating an x1, x4 device
• Sending packet with incorrect “running disparity”
• TX framing errors on TLPs
Data Link Layer
• Sending packets with incorrect LCRC
• Programmatically answers NAK instead of ACK, for retry buffer test
• Wrong sequence numbers
Transaction Layer
• Arbitrary header field contents
• Sending “nullified TLPs”
• Sending “poisoned TLPs”
• Advertised packet length (in TLP header) different from actual packet
length (by one DWord)
• The transmitter ignores flow control credits
• Completion loss/delay
Configuration Space Features
• Can emulate the configuration of different types of PCI Express devices
• Supports up to 6 base address registers and expansion ROM decoder
• Full support for PCI Header type 0 configuration space
• Supported Capability Structures:
– PCI power management capability structure
– MSI capability structure
– PCI Express capability structure
• Virtual Channel capability structure
LTSSM Exerciser
Display Features
• Explorer like tree structure to select test
• Display of test log in GUI
• Feedback of state transitions performed
• Timestamp in [ns] for all states
• Link status indications
• Link width x1, x4, x8, x16
Debug Support Features
• External trigger on exit from L0
• Log file output of LTSSM-Exerciser state transitions and Timestamps
• Automatic flow control initialization with infinite credits
Supported States
• Detect
• Polling
• Configuration
• L0
• Recovery
Error injection
• Pre-defined test cases for recovery state
Specification for E2960A
Protocol Exerciser
• Generates and responds to PCI Express packets and packet sequences
• GUI, DCOM application programming interface, TCL interfaces and
in-system port control
• Error insertion lets you test corner cases and failure behavior
• Simulate or emulate an PCI Express end node
Perform Realistic Tests with Device Emulation
• Simulate various test scenarios by setting exerciser parameters the way
you want
• Minimize the number of real devices needed to create a large-scale test
environment
• 2 MB data memory allows you to emulate PCI Express end nodes
• Easily record packets from the protocol analyzer and replay with the
exerciser as many times as you want. Use drag and drop or copy and
paste functionality or export files from the protocol analyzer
• Use external trigger in/out for cross triggering, event triggering
and triggering another device/instrument for more thorough
troubleshooting
• Real-time data compare feature allows you to check the integrity of your
data to give you more confidence in your results
Increase Test Coverage with Configurable Traffic Generation
• Transmit and receive PCI Express traffic at full bandwidth of x1, x2, x4
and x8 link widths with 2.5 Gbps
• Customize the traffic you send: Generate requests with parameters and
behaviors you define
• Use a wide range of real-world traffic conditions
• Validate the boundary conditions of your system
• Generate any combination of PCI Express packets for multiple ports and
correlate the test results across time for comprehensive system testing
• Stress your system to the max: test your system under worst-case
conditions and see how devices act during error conditions
• Algorithmic data generation/checking feature allows you to compare-
incoming packet payload against algorithmically generated reference
data
• Fully configurable configuration space, including PCI Express extended
capabilities
Real-time Statistics Help you See Immediate Changes in your System’s
Performance
• Real-time performance counters
Customize your Measurements with Test Automation and Scripting
Capabilities
• Control software via the easy-to-use graphical user interface, program-
matically through DCOM or TCL interfaces and via an in-system port (via
system under test)
• Create and automate your test procedure to eliminate tedious manual
testing
• Repeat tests for subsequent product builds
• Protocol checker automatically checks 23 protocol rules based on the
PCI Express specification
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