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English URL
www.agilent.com/find/products
E2960A
E2960B
E2960 Series for PCI Express 1.0 and 2.0 (cont.)
System and Protocol Test
E2960A/B Probing Options
The E2960A/B analyzer offers various different probing options to
support PCI Express 1.0 and 2.0 probing. Beside others, the probing
options comprise interposer probing, midbus probing, express card
and flying leads.
The Agilent midbus 2.0 series of probes using soft touch tech-
nology gives insight to the system without influencing it. It is a non-
intrusive and passive probing option, providing extremely low
capacitive loading (less than 150 fF). The Agilent Midbus 2.0 probing
solution is available to support various layout requirements and
needs.
P2L for Full System Viewing
The P2L gateway enables connecting to the Agilent Logic Analyzer to
do time correlated cross bus measurements and cross triggering.
Both Logic Analyzer and Protocol Analyzer instruments can be
operated from a single PC.
E2960A/B Protocol Exerciser for PCI Express lets you Test
and Validate your System’s Performance under Varied
Conditions
With its fully adjustable parameters, the E2960A/B protocol exer-
ciser lets you emulate any PCI Express design. Furthermore it is
capable to generate and respond to any PCI Express packet or
sequences of packets. It is an intelligent I/O communication tool that
can react as a PCI Express end node or root complex. The E2960A/B
exerciser’s functionality extends far beyond the capabilities of a
simple packet generator. It is tailored to validate corner cases and
emulate stress conditions for components on system boards and
add-in cards. The protocol exerciser is the ideal tool to test and vali-
date x1 up to x16 PCI Express designs.
The E2960A/B exerciser lets you stress all data paths in your
system so you can force it to fail. You can also insert errors and test
the behavior of designs in response to these errors to enable worst-
case-scenario testing.
Using the x1 through x 16 LTSSM exerciser (Link Training and
Status State Machine) training sequences and ordered sets can be
generated across all the lane widths, enabling effective testing of the
link negotiation and supporting dynamic lane width changes.
Using the passive backplane, you can verify your device in a
controlled environment that gives you a quite PCI Express bus inde-
pendent of a system. The passive backplane features 3 independent
busses, all prepared for traffic up to x16 and includes reset, standby
power, SSC etc.
N2X Platform Continuity
The E2960A/B protocol analyzer and exerciser for PCI Express are
based on the modular system tester platform with Agilent’s N2X
technology. The universal and upgradeable platform offers multi-
protocol and time correlated test/cross bus analysis support for ASI,
PCI Express and Fibre Channel applications and protects capital
investment. Components from one generation can be reused in the
next generation.
The complete software including the GUI is also the same for
both series of products, so customers can protect their investment
and leverage their existing know-how to start PCIe 2.0 testing imme-
diately.
The APIs are backward compatible so that previously devel-
oped scripts can be reused.
Powerful Triggering, Easy Setup
The protocol analyzer’s sophisticated trigger capabilities are based
on a trigger sequencer. It offers an easy-to-use set up and graphical
representation of the trigger sequence. Examples and listed prede-
fined conditions reduce time-consuming trigger setups. You can
define up to 8 states, 8 patterns and 2 counters with various actions
store, increment counter, trigger out and so on.
Specifications
Specification for E2960B Protocol Analyzer
Display Features
• Highly configurable GUI, based on a configurable tabular view
• Color Customization
• Condensed data view using context sensitive columns
• “Ping-Pong” view of upstream/downstream data with Easy Flow
• Easy navigation within captured trace
• Traffic overview (post capture)
• Per lane display to display data of individual lanes
• Record decode and single line view
• Expand and collapse packets in order to obtain more information
Packets with errors are highlighted
• Colour-coded transaction types allow easy recognition of various types
of traffic
• Multiple markers with comment functionality
• Display with time-stamps
Trigger Features
• Graphical trigger setup
• Trigger sequencer with up to:
– 8 states
– 2 counters/timers
– 4 pattern terms
– External trigger in and out
– Protocol error trigger (disparity error and invalid 10b symbols)
– Multi-way branching
• Filtering (real time):
– Idles
– On a per-packet basis controlled by the trigger sequencer
– Filter conditions can be defined individually for each trigger
sequencer state
– Storage qualification
– Trigger on payload (first 1 or 2 dwords)
Traffic Capture Features
• Supports capturing in x1, x2, x4, x8, x16 link width with 2.5 GT/s and
5 GT/s
• Non-intrusive traffic capturing
• Captures training sequences, ordered sets, data-link-layer packets and
transaction-layer packets in both directions simultaneously
• Supports data rates 2.5 GT/s and 5 GT/s (±300 ppm)
• Error detection
• Disparity errors and invalid 10b symbols in hardware
• LCRC, symbol, disparity, EDB, framing, idle data Malformed packet
check (CRC error, invalid field contents, length mismatch) in software
Other Features
• Analyzer to exerciser traffic record and replay
• Example triggers se programming examples
• Timestamps with 8 ns resolution (absolute and relative)
• Automatic lane polarity detection
• 1 GB trace memory
• Latency measurements (using markers)
• External trigger in/out
Exerciser Physical Layer
• Fully automated symbol encoding/decoding, and generation and
validation of packet framing; ability to report framing errors to user
• Scrambling can be turned on or off by user
• Configurable, automatic link initialization and training:
– Automatic Lane Polarity Detection (RX), separate for each lane
– Programmable Lane Polarity Inversion (TX), separate for
each lane
– Automatic link width negotiation; link widths x1, x4 supported;
user can configure which widths will be negotiated during
link training
– Programmable Lane Reversal (TX, RX automatic)
– Programmable Lane Skew: (±7 symbols, resolution:
1 symbol time)
• Link Training and Status State Machine: Full support for states Detect,
Polling, Configuration, Recovery, L1, L0s, L0
• Programmable skip rate and number of SKPs per skip OS
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