SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
38
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www.acromag.com
Double select the Zynq Ult block
Select => Switch to Advanced Mode
Review the contents of the block diagram. The green colored blocks in the
diagram are configurable.
Select => I/O Configuration
Notice that the MIO voltages listed correspond to the voltages supplied to
these MIO banks of the design schematics. Bank 500 MIO 0 to 25 is
powered by 3.3 volts, bank 501 MIO 26 to 51 is powered by 3.3 volts, bank
502 MIO 52 to 77 is powered by 1.8 volts, and bank 503 is powered by 1.8
volts.
Also notice the peripherals enabled include QSPI (using MIO pins 0 to 5), SD
card (using MIO pins 13 to 24), I2C (using MIO pins 8 and 9), GPO5 MIO37,
UART 1 (using MIO pins 44 and 45), GEM3 MIO64 to 75, USB 0 MIO52 to 63,
one lane PCIe with reset on MIO pin 30.
Select Clock Configuration to review the various clock frequencies.
Select DDR Configuration to review configuration setting corresponding the
low power DDR4 device.
Select PS-PL Configuration and notice that the processor system to
programmable logic interface uses one AXI Master Interface. This master
interface link to the AXI interconnect slave interfaces configured above.
Double click UART 1 canvas to access the UART 1 options.
Notice the blocks checked below correspond with those enabled for
operation in their corresponding configuration dialog.
