SERIES APZU+ ACROPACK
USER’S MANUAL
Acromag, Inc. Tel: 248-295-0310 -
32
-
www.acromag.com
5.1 Vivado and the Programmable Logic
You can use the Vivado Design Suite tools to add design sources to your
hardware. These include the IP integrator, which simplifies the process of
adding IP to your existing project and creating connections for ports (such as
clock and reset).
You can accomplish all your hardware system development using the Vivado
tools along with IP integrator. This includes specification of the Zynq
Ult Processing System, peripherals, and the interconnection of these
components, along with their respective detailed configuration.
Acromag provides an FPGA generated firmware example design that
provides host access to the hardware digital I/O on the AP module. The
example design is intended to be a starting point from which customers will
develop their customized applications. The example design is implemented
using the Xilinx Vivado development environment.
The Programmable Logic Section, in addition to the programmable logic
cells, also comes integrated with few high performance peripherals,
including the following:
System Monitor, BRAM, and custom I/O interface with interrupts.
5.1.1 APZU Programmable Logic Block Diagram Overview
In this example we are using an APZU board and
Vitis 2020.1 software
development platform
.
Open that project in Vivado.
Select
Start => All Programs => Xilinx Design Tools => Vivado 2020.1
Under Quick Start Select
Open Project >
and then browse to the folder
containing the project file AcroPackZynq.xpr.
Select AcroPackZynq.xpr file and then select=> OK
